191 lines
8.2 KiB
C
191 lines
8.2 KiB
C
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/* SPDX-License-Identifier: GPL-2.0 */
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#ifndef _SPRD_DMA_H_
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#define _SPRD_DMA_H_
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#define SPRD_DMA_REQ_SHIFT 8
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#define SPRD_DMA_TRG_MODE_SHIFT 16
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#define SPRD_DMA_CHN_MODE_SHIFT 24
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#define SPRD_DMA_FLAGS(chn_mode, trg_mode, req_mode, int_type) \
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((chn_mode) << SPRD_DMA_CHN_MODE_SHIFT | \
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(trg_mode) << SPRD_DMA_TRG_MODE_SHIFT | \
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(req_mode) << SPRD_DMA_REQ_SHIFT | (int_type))
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/*
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* The Spreadtrum DMA controller supports channel 2-stage tansfer, that means
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* we can request 2 dma channels, one for source channel, and another one for
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* destination channel. Each channel is independent, and has its own
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* configurations. Once the source channel's transaction is done, it will
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* trigger the destination channel's transaction automatically by hardware
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* signal.
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*
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* To support 2-stage tansfer, we must configure the channel mode and trigger
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* mode as below definition.
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*/
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/*
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* enum sprd_dma_chn_mode: define the DMA channel mode for 2-stage transfer
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* @SPRD_DMA_CHN_MODE_NONE: No channel mode setting which means channel doesn't
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* support the 2-stage transfer.
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* @SPRD_DMA_SRC_CHN0: Channel used as source channel 0.
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* @SPRD_DMA_SRC_CHN1: Channel used as source channel 1.
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* @SPRD_DMA_DST_CHN0: Channel used as destination channel 0.
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* @SPRD_DMA_DST_CHN1: Channel used as destination channel 1.
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*
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* Now the DMA controller can supports 2 groups 2-stage transfer.
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*/
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enum sprd_dma_chn_mode {
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SPRD_DMA_CHN_MODE_NONE,
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SPRD_DMA_SRC_CHN0,
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SPRD_DMA_SRC_CHN1,
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SPRD_DMA_DST_CHN0,
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SPRD_DMA_DST_CHN1,
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};
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/*
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* enum sprd_dma_trg_mode: define the DMA channel trigger mode for 2-stage
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* transfer
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* @SPRD_DMA_NO_TRG: No trigger setting.
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* @SPRD_DMA_FRAG_DONE_TRG: Trigger the transaction of destination channel
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* automatically once the source channel's fragment request is done.
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* @SPRD_DMA_BLOCK_DONE_TRG: Trigger the transaction of destination channel
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* automatically once the source channel's block request is done.
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* @SPRD_DMA_TRANS_DONE_TRG: Trigger the transaction of destination channel
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* automatically once the source channel's transfer request is done.
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* @SPRD_DMA_LIST_DONE_TRG: Trigger the transaction of destination channel
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* automatically once the source channel's link-list request is done.
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*/
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enum sprd_dma_trg_mode {
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SPRD_DMA_NO_TRG,
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SPRD_DMA_FRAG_DONE_TRG,
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SPRD_DMA_BLOCK_DONE_TRG,
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SPRD_DMA_TRANS_DONE_TRG,
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SPRD_DMA_LIST_DONE_TRG,
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};
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/*
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* enum sprd_dma_req_mode: define the DMA request mode
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* @SPRD_DMA_FRAG_REQ: fragment request mode
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* @SPRD_DMA_BLK_REQ: block request mode
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* @SPRD_DMA_TRANS_REQ: transaction request mode
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* @SPRD_DMA_LIST_REQ: link-list request mode
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*
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* We have 4 types request mode: fragment mode, block mode, transaction mode
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* and linklist mode. One transaction can contain several blocks, one block can
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* contain several fragments. Link-list mode means we can save several DMA
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* configuration into one reserved memory, then DMA can fetch each DMA
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* configuration automatically to start transfer.
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*/
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enum sprd_dma_req_mode {
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SPRD_DMA_FRAG_REQ,
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SPRD_DMA_BLK_REQ,
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SPRD_DMA_TRANS_REQ,
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SPRD_DMA_LIST_REQ,
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};
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/*
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* enum sprd_dma_int_type: define the DMA interrupt type
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* @SPRD_DMA_NO_INT: do not need generate DMA interrupts.
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* @SPRD_DMA_FRAG_INT: fragment done interrupt when one fragment request
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* is done.
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* @SPRD_DMA_BLK_INT: block done interrupt when one block request is done.
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* @SPRD_DMA_BLK_FRAG_INT: block and fragment interrupt when one fragment
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* or one block request is done.
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* @SPRD_DMA_TRANS_INT: tansaction done interrupt when one transaction
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* request is done.
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* @SPRD_DMA_TRANS_FRAG_INT: transaction and fragment interrupt when one
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* transaction request or fragment request is done.
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* @SPRD_DMA_TRANS_BLK_INT: transaction and block interrupt when one
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* transaction request or block request is done.
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* @SPRD_DMA_LIST_INT: link-list done interrupt when one link-list request
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* is done.
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* @SPRD_DMA_CFGERR_INT: configure error interrupt when configuration is
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* incorrect.
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*/
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enum sprd_dma_int_type {
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SPRD_DMA_NO_INT,
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SPRD_DMA_FRAG_INT,
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SPRD_DMA_BLK_INT,
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SPRD_DMA_BLK_FRAG_INT,
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SPRD_DMA_TRANS_INT,
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SPRD_DMA_TRANS_FRAG_INT,
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SPRD_DMA_TRANS_BLK_INT,
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SPRD_DMA_LIST_INT,
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SPRD_DMA_CFGERR_INT,
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};
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/*
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* struct sprd_dma_linklist - DMA link-list address structure
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* @virt_addr: link-list virtual address to configure link-list node
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* @phy_addr: link-list physical address to link DMA transfer
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* @wrap_addr: the wrap address for link-list mode, which means once the
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* transfer address reaches the wrap address, the next transfer address
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* will jump to the address specified by wrap_to register.
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*
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* The Spreadtrum DMA controller supports the link-list mode, that means slaves
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* can supply several groups configurations (each configuration represents one
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* DMA transfer) saved in memory, and DMA controller will link these groups
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* configurations by writing the physical address of each configuration into the
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* link-list register.
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*
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* Just as shown below, the link-list pointer register will be pointed to the
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* physical address of 'configuration 1', and the 'configuration 1' link-list
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* pointer will be pointed to 'configuration 2', and so on.
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* Once trigger the DMA transfer, the DMA controller will load 'configuration
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* 1' to its registers automatically, after 'configuration 1' transaction is
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* done, DMA controller will load 'configuration 2' automatically, until all
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* DMA transactions are done.
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*
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* Note: The last link-list pointer should point to the physical address
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* of 'configuration 1', which can avoid DMA controller loads incorrect
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* configuration when the last configuration transaction is done.
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*
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* DMA controller linklist memory
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* ====================== -----------------------
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*| | | configuration 1 |<---
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*| DMA controller | ------->| | |
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*| | | | | |
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*| | | | | |
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*| | | | | |
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*| linklist pointer reg |---- ----| linklist pointer | |
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* ====================== | ----------------------- |
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* | |
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* | ----------------------- |
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* | | configuration 2 | |
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* --->| | |
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* | | |
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* | | |
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* | | |
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* ----| linklist pointer | |
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* | ----------------------- |
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* | |
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* | ----------------------- |
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* | | configuration 3 | |
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* --->| | |
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* | | |
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* | . | |
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* . |
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* . |
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* . |
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* | . |
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* | ----------------------- |
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* | | configuration n | |
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* --->| | |
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* | | |
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* | | |
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* | | |
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* | linklist pointer |----
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* -----------------------
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*
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* To support the link-list mode, DMA slaves should allocate one segment memory
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* from always-on IRAM or dma coherent memory to store these groups of DMA
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* configuration, and pass the virtual and physical address to DMA controller.
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*/
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struct sprd_dma_linklist {
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unsigned long virt_addr;
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phys_addr_t phy_addr;
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phys_addr_t wrap_addr;
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};
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#endif
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