98 lines
3.3 KiB
C
98 lines
3.3 KiB
C
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/* SPDX-License-Identifier: GPL-2.0 */
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/* Copyright (C) 2017 Intel Corporation */
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/* Functions to access TPS68470 power management chip. */
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#ifndef __LINUX_MFD_TPS68470_H
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#define __LINUX_MFD_TPS68470_H
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/* Register addresses */
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#define TPS68470_REG_POSTDIV2 0x06
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#define TPS68470_REG_BOOSTDIV 0x07
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#define TPS68470_REG_BUCKDIV 0x08
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#define TPS68470_REG_PLLSWR 0x09
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#define TPS68470_REG_XTALDIV 0x0A
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#define TPS68470_REG_PLLDIV 0x0B
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#define TPS68470_REG_POSTDIV 0x0C
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#define TPS68470_REG_PLLCTL 0x0D
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#define TPS68470_REG_PLLCTL2 0x0E
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#define TPS68470_REG_CLKCFG1 0x0F
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#define TPS68470_REG_CLKCFG2 0x10
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#define TPS68470_REG_GPCTL0A 0x14
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#define TPS68470_REG_GPCTL0B 0x15
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#define TPS68470_REG_GPCTL1A 0x16
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#define TPS68470_REG_GPCTL1B 0x17
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#define TPS68470_REG_GPCTL2A 0x18
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#define TPS68470_REG_GPCTL2B 0x19
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#define TPS68470_REG_GPCTL3A 0x1A
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#define TPS68470_REG_GPCTL3B 0x1B
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#define TPS68470_REG_GPCTL4A 0x1C
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#define TPS68470_REG_GPCTL4B 0x1D
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#define TPS68470_REG_GPCTL5A 0x1E
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#define TPS68470_REG_GPCTL5B 0x1F
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#define TPS68470_REG_GPCTL6A 0x20
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#define TPS68470_REG_GPCTL6B 0x21
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#define TPS68470_REG_SGPO 0x22
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#define TPS68470_REG_GPDI 0x26
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#define TPS68470_REG_GPDO 0x27
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#define TPS68470_REG_VCMVAL 0x3C
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#define TPS68470_REG_VAUX1VAL 0x3D
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#define TPS68470_REG_VAUX2VAL 0x3E
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#define TPS68470_REG_VIOVAL 0x3F
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#define TPS68470_REG_VSIOVAL 0x40
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#define TPS68470_REG_VAVAL 0x41
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#define TPS68470_REG_VDVAL 0x42
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#define TPS68470_REG_S_I2C_CTL 0x43
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#define TPS68470_REG_VCMCTL 0x44
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#define TPS68470_REG_VAUX1CTL 0x45
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#define TPS68470_REG_VAUX2CTL 0x46
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#define TPS68470_REG_VACTL 0x47
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#define TPS68470_REG_VDCTL 0x48
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#define TPS68470_REG_RESET 0x50
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#define TPS68470_REG_REVID 0xFF
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#define TPS68470_REG_MAX TPS68470_REG_REVID
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/* Register field definitions */
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#define TPS68470_REG_RESET_MASK GENMASK(7, 0)
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#define TPS68470_VAVAL_AVOLT_MASK GENMASK(6, 0)
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#define TPS68470_VDVAL_DVOLT_MASK GENMASK(5, 0)
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#define TPS68470_VCMVAL_VCVOLT_MASK GENMASK(6, 0)
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#define TPS68470_VIOVAL_IOVOLT_MASK GENMASK(6, 0)
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#define TPS68470_VSIOVAL_IOVOLT_MASK GENMASK(6, 0)
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#define TPS68470_VAUX1VAL_AUX1VOLT_MASK GENMASK(6, 0)
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#define TPS68470_VAUX2VAL_AUX2VOLT_MASK GENMASK(6, 0)
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#define TPS68470_VACTL_EN_MASK GENMASK(0, 0)
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#define TPS68470_VDCTL_EN_MASK GENMASK(0, 0)
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#define TPS68470_VCMCTL_EN_MASK GENMASK(0, 0)
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#define TPS68470_S_I2C_CTL_EN_MASK GENMASK(1, 0)
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#define TPS68470_VAUX1CTL_EN_MASK GENMASK(0, 0)
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#define TPS68470_VAUX2CTL_EN_MASK GENMASK(0, 0)
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#define TPS68470_PLL_EN_MASK GENMASK(0, 0)
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#define TPS68470_CLKCFG1_MODE_A_MASK GENMASK(1, 0)
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#define TPS68470_CLKCFG1_MODE_B_MASK GENMASK(3, 2)
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#define TPS68470_CLKCFG2_DRV_STR_2MA 0x05
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#define TPS68470_PLL_OUTPUT_ENABLE 0x02
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#define TPS68470_CLK_SRC_XTAL BIT(0)
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#define TPS68470_PLLSWR_DEFAULT GENMASK(1, 0)
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#define TPS68470_OSC_EXT_CAP_DEFAULT 0x05
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#define TPS68470_OUTPUT_A_SHIFT 0x00
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#define TPS68470_OUTPUT_B_SHIFT 0x02
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#define TPS68470_CLK_SRC_SHIFT GENMASK(2, 0)
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#define TPS68470_OSC_EXT_CAP_SHIFT BIT(2)
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#define TPS68470_GPIO_CTL_REG_A(x) (TPS68470_REG_GPCTL0A + (x) * 2)
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#define TPS68470_GPIO_CTL_REG_B(x) (TPS68470_REG_GPCTL0B + (x) * 2)
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#define TPS68470_GPIO_MODE_MASK GENMASK(1, 0)
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#define TPS68470_GPIO_MODE_IN 0
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#define TPS68470_GPIO_MODE_IN_PULLUP 1
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#define TPS68470_GPIO_MODE_OUT_CMOS 2
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#define TPS68470_GPIO_MODE_OUT_ODRAIN 3
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#endif /* __LINUX_MFD_TPS68470_H */
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