2023-08-30 17:31:07 +02:00
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/* SPDX-License-Identifier: GPL-2.0 */
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/*
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* Copyright (C) 2009 Samsung Electronics Ltd.
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* Jaswinder Singh <jassi.brar@samsung.com>
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*/
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#ifndef __SPI_S3C64XX_H
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#define __SPI_S3C64XX_H
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#include <linux/dmaengine.h>
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struct platform_device;
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/**
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* struct s3c64xx_spi_csinfo - ChipSelect description
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* @fb_delay: Slave specific feedback delay.
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* Refer to FB_CLK_SEL register definition in SPI chapter.
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*
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* This is per SPI-Slave Chipselect information.
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* Allocate and initialize one in machine init code and make the
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* spi_board_info.controller_data point to it.
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*/
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struct s3c64xx_spi_csinfo {
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u8 fb_delay;
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};
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/**
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* struct s3c64xx_spi_info - SPI Controller defining structure
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* @src_clk_nr: Clock source index for the CLK_CFG[SPI_CLKSEL] field.
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* @num_cs: Number of CS this controller emulates.
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2023-10-24 12:59:35 +02:00
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* @no_cs: Used when CS line is not connected.
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2023-08-30 17:31:07 +02:00
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* @cfg_gpio: Configure pins for this SPI controller.
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*/
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struct s3c64xx_spi_info {
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int src_clk_nr;
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int num_cs;
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bool no_cs;
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2023-10-24 12:59:35 +02:00
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bool polling;
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2023-08-30 17:31:07 +02:00
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int (*cfg_gpio)(void);
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};
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/**
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* s3c64xx_spi_set_platdata - SPI Controller configure callback by the board
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* initialization code.
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* @src_clk_nr: Clock the SPI controller is to use to generate SPI clocks.
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* @num_cs: Number of elements in the 'cs' array.
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*
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* Call this from machine init code for each SPI Controller that
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* has some chips attached to it.
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*/
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extern void s3c64xx_spi0_set_platdata(int src_clk_nr, int num_cs);
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/* defined by architecture to configure gpio */
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extern int s3c64xx_spi0_cfg_gpio(void);
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extern struct s3c64xx_spi_info s3c64xx_spi0_pdata;
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#endif /*__SPI_S3C64XX_H */
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