67 lines
1.6 KiB
C
67 lines
1.6 KiB
C
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/* SPDX-License-Identifier: GPL-2.0 */
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/*
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* Copyright (c) 2022 Amlogic, Inc. All rights reserved.
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*/
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#ifndef __MESON_DDR_PMU_H__
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#define __MESON_DDR_PMU_H__
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#define MAX_CHANNEL_NUM 8
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enum {
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ALL_CHAN_COUNTER_ID,
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CHAN1_COUNTER_ID,
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CHAN2_COUNTER_ID,
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CHAN3_COUNTER_ID,
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CHAN4_COUNTER_ID,
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CHAN5_COUNTER_ID,
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CHAN6_COUNTER_ID,
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CHAN7_COUNTER_ID,
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CHAN8_COUNTER_ID,
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COUNTER_MAX_ID,
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};
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struct dmc_info;
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struct dmc_counter {
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u64 all_cnt; /* The count of all requests come in/out ddr controller */
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union {
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u64 all_req;
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struct {
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u64 all_idle_cnt;
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u64 all_16bit_cnt;
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};
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};
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u64 channel_cnt[MAX_CHANNEL_NUM]; /* To save a DMC bandwidth-monitor channel counter */
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};
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struct dmc_hw_info {
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void (*enable)(struct dmc_info *info);
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void (*disable)(struct dmc_info *info);
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/* Bind an axi line to a bandwidth-monitor channel */
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void (*set_axi_filter)(struct dmc_info *info, int axi_id, int chann);
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int (*irq_handler)(struct dmc_info *info,
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struct dmc_counter *counter);
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void (*get_counters)(struct dmc_info *info,
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struct dmc_counter *counter);
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int dmc_nr; /* The number of dmc controller */
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int chann_nr; /* The number of dmc bandwidth monitor channels */
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struct attribute **fmt_attr;
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const u64 capability[2];
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};
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struct dmc_info {
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const struct dmc_hw_info *hw_info;
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void __iomem *ddr_reg[4];
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unsigned long timer_value; /* Timer value in TIMER register */
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void __iomem *pll_reg;
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int irq_num; /* irq vector number */
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};
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int meson_ddr_pmu_create(struct platform_device *pdev);
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int meson_ddr_pmu_remove(struct platform_device *pdev);
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#endif /* __MESON_DDR_PMU_H__ */
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