363 lines
11 KiB
C
363 lines
11 KiB
C
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// SPDX-License-Identifier: GPL-2.0-only
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//
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// Components shared between ASoC and HDA CS35L56 drivers
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//
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// Copyright (C) 2023 Cirrus Logic, Inc. and
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// Cirrus Logic International Semiconductor Ltd.
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#include <linux/regmap.h>
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#include <linux/regulator/consumer.h>
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#include <linux/types.h>
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#include "cs35l56.h"
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static const struct reg_default cs35l56_reg_defaults[] = {
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{ CS35L56_ASP1_ENABLES1, 0x00000000 },
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{ CS35L56_ASP1_CONTROL1, 0x00000028 },
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{ CS35L56_ASP1_CONTROL2, 0x18180200 },
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{ CS35L56_ASP1_CONTROL3, 0x00000002 },
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{ CS35L56_ASP1_FRAME_CONTROL1, 0x03020100 },
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{ CS35L56_ASP1_FRAME_CONTROL5, 0x00020100 },
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{ CS35L56_ASP1_DATA_CONTROL1, 0x00000018 },
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{ CS35L56_ASP1_DATA_CONTROL5, 0x00000018 },
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{ CS35L56_ASP1TX1_INPUT, 0x00000018 },
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{ CS35L56_ASP1TX2_INPUT, 0x00000019 },
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{ CS35L56_ASP1TX3_INPUT, 0x00000020 },
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{ CS35L56_ASP1TX4_INPUT, 0x00000028 },
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{ CS35L56_SWIRE_DP3_CH1_INPUT, 0x00000018 },
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{ CS35L56_SWIRE_DP3_CH2_INPUT, 0x00000019 },
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{ CS35L56_SWIRE_DP3_CH3_INPUT, 0x00000029 },
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{ CS35L56_SWIRE_DP3_CH4_INPUT, 0x00000028 },
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{ CS35L56_IRQ1_CFG, 0x00000000 },
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{ CS35L56_IRQ1_MASK_1, 0x83ffffff },
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{ CS35L56_IRQ1_MASK_2, 0xffff7fff },
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{ CS35L56_IRQ1_MASK_4, 0xe0ffffff },
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{ CS35L56_IRQ1_MASK_8, 0xfc000fff },
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{ CS35L56_IRQ1_MASK_18, 0x1f7df0ff },
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{ CS35L56_IRQ1_MASK_20, 0x15c00000 },
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/* CS35L56_MAIN_RENDER_USER_MUTE - soft register, no default */
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/* CS35L56_MAIN_RENDER_USER_VOLUME - soft register, no default */
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/* CS35L56_MAIN_POSTURE_NUMBER - soft register, no default */
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};
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static bool cs35l56_is_dsp_memory(unsigned int reg)
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{
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switch (reg) {
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case CS35L56_DSP1_XMEM_PACKED_0 ... CS35L56_DSP1_XMEM_PACKED_6143:
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case CS35L56_DSP1_XMEM_UNPACKED32_0 ... CS35L56_DSP1_XMEM_UNPACKED32_4095:
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case CS35L56_DSP1_XMEM_UNPACKED24_0 ... CS35L56_DSP1_XMEM_UNPACKED24_8191:
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case CS35L56_DSP1_YMEM_PACKED_0 ... CS35L56_DSP1_YMEM_PACKED_4604:
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case CS35L56_DSP1_YMEM_UNPACKED32_0 ... CS35L56_DSP1_YMEM_UNPACKED32_3070:
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case CS35L56_DSP1_YMEM_UNPACKED24_0 ... CS35L56_DSP1_YMEM_UNPACKED24_6141:
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case CS35L56_DSP1_PMEM_0 ... CS35L56_DSP1_PMEM_5114:
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return true;
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default:
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return false;
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}
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}
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static bool cs35l56_readable_reg(struct device *dev, unsigned int reg)
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{
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switch (reg) {
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case CS35L56_DEVID:
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case CS35L56_REVID:
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case CS35L56_RELID:
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case CS35L56_OTPID:
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case CS35L56_SFT_RESET:
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case CS35L56_GLOBAL_ENABLES:
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case CS35L56_BLOCK_ENABLES:
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case CS35L56_BLOCK_ENABLES2:
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case CS35L56_REFCLK_INPUT:
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case CS35L56_GLOBAL_SAMPLE_RATE:
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case CS35L56_ASP1_ENABLES1:
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case CS35L56_ASP1_CONTROL1:
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case CS35L56_ASP1_CONTROL2:
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case CS35L56_ASP1_CONTROL3:
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case CS35L56_ASP1_FRAME_CONTROL1:
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case CS35L56_ASP1_FRAME_CONTROL5:
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case CS35L56_ASP1_DATA_CONTROL1:
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case CS35L56_ASP1_DATA_CONTROL5:
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case CS35L56_DACPCM1_INPUT:
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case CS35L56_DACPCM2_INPUT:
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case CS35L56_ASP1TX1_INPUT:
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case CS35L56_ASP1TX2_INPUT:
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case CS35L56_ASP1TX3_INPUT:
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case CS35L56_ASP1TX4_INPUT:
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case CS35L56_DSP1RX1_INPUT:
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case CS35L56_DSP1RX2_INPUT:
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case CS35L56_SWIRE_DP3_CH1_INPUT:
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case CS35L56_SWIRE_DP3_CH2_INPUT:
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case CS35L56_SWIRE_DP3_CH3_INPUT:
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case CS35L56_SWIRE_DP3_CH4_INPUT:
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case CS35L56_IRQ1_CFG:
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case CS35L56_IRQ1_STATUS:
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case CS35L56_IRQ1_EINT_1 ... CS35L56_IRQ1_EINT_8:
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case CS35L56_IRQ1_EINT_18:
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case CS35L56_IRQ1_EINT_20:
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case CS35L56_IRQ1_MASK_1:
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case CS35L56_IRQ1_MASK_2:
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case CS35L56_IRQ1_MASK_4:
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case CS35L56_IRQ1_MASK_8:
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case CS35L56_IRQ1_MASK_18:
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case CS35L56_IRQ1_MASK_20:
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case CS35L56_DSP_VIRTUAL1_MBOX_1:
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case CS35L56_DSP_VIRTUAL1_MBOX_2:
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case CS35L56_DSP_VIRTUAL1_MBOX_3:
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case CS35L56_DSP_VIRTUAL1_MBOX_4:
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case CS35L56_DSP_VIRTUAL1_MBOX_5:
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case CS35L56_DSP_VIRTUAL1_MBOX_6:
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case CS35L56_DSP_VIRTUAL1_MBOX_7:
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case CS35L56_DSP_VIRTUAL1_MBOX_8:
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case CS35L56_DSP_RESTRICT_STS1:
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case CS35L56_DSP1_SYS_INFO_ID ... CS35L56_DSP1_SYS_INFO_END:
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case CS35L56_DSP1_AHBM_WINDOW_DEBUG_0:
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case CS35L56_DSP1_AHBM_WINDOW_DEBUG_1:
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case CS35L56_DSP1_SCRATCH1:
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case CS35L56_DSP1_SCRATCH2:
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case CS35L56_DSP1_SCRATCH3:
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case CS35L56_DSP1_SCRATCH4:
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return true;
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default:
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return cs35l56_is_dsp_memory(reg);
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}
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}
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static bool cs35l56_precious_reg(struct device *dev, unsigned int reg)
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{
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switch (reg) {
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case CS35L56_DSP1_XMEM_PACKED_0 ... CS35L56_DSP1_XMEM_PACKED_6143:
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case CS35L56_DSP1_YMEM_PACKED_0 ... CS35L56_DSP1_YMEM_PACKED_4604:
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case CS35L56_DSP1_PMEM_0 ... CS35L56_DSP1_PMEM_5114:
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return true;
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default:
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return false;
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}
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}
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static bool cs35l56_volatile_reg(struct device *dev, unsigned int reg)
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{
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switch (reg) {
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case CS35L56_DEVID:
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case CS35L56_REVID:
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case CS35L56_RELID:
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case CS35L56_OTPID:
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case CS35L56_SFT_RESET:
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case CS35L56_GLOBAL_ENABLES: /* owned by firmware */
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case CS35L56_BLOCK_ENABLES: /* owned by firmware */
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case CS35L56_BLOCK_ENABLES2: /* owned by firmware */
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case CS35L56_REFCLK_INPUT: /* owned by firmware */
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case CS35L56_GLOBAL_SAMPLE_RATE: /* owned by firmware */
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case CS35L56_DACPCM1_INPUT: /* owned by firmware */
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case CS35L56_DACPCM2_INPUT: /* owned by firmware */
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case CS35L56_DSP1RX1_INPUT: /* owned by firmware */
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case CS35L56_DSP1RX2_INPUT: /* owned by firmware */
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case CS35L56_IRQ1_STATUS:
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case CS35L56_IRQ1_EINT_1 ... CS35L56_IRQ1_EINT_8:
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case CS35L56_IRQ1_EINT_18:
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case CS35L56_IRQ1_EINT_20:
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case CS35L56_DSP_VIRTUAL1_MBOX_1:
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case CS35L56_DSP_VIRTUAL1_MBOX_2:
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case CS35L56_DSP_VIRTUAL1_MBOX_3:
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case CS35L56_DSP_VIRTUAL1_MBOX_4:
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case CS35L56_DSP_VIRTUAL1_MBOX_5:
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case CS35L56_DSP_VIRTUAL1_MBOX_6:
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case CS35L56_DSP_VIRTUAL1_MBOX_7:
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case CS35L56_DSP_VIRTUAL1_MBOX_8:
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case CS35L56_DSP_RESTRICT_STS1:
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case CS35L56_DSP1_SYS_INFO_ID ... CS35L56_DSP1_SYS_INFO_END:
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case CS35L56_DSP1_AHBM_WINDOW_DEBUG_0:
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case CS35L56_DSP1_AHBM_WINDOW_DEBUG_1:
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case CS35L56_DSP1_SCRATCH1:
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case CS35L56_DSP1_SCRATCH2:
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case CS35L56_DSP1_SCRATCH3:
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case CS35L56_DSP1_SCRATCH4:
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return true;
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case CS35L56_MAIN_RENDER_USER_MUTE:
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case CS35L56_MAIN_RENDER_USER_VOLUME:
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case CS35L56_MAIN_POSTURE_NUMBER:
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return false;
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default:
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return cs35l56_is_dsp_memory(reg);
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}
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}
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static const u32 cs35l56_firmware_registers[] = {
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CS35L56_MAIN_RENDER_USER_MUTE,
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CS35L56_MAIN_RENDER_USER_VOLUME,
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CS35L56_MAIN_POSTURE_NUMBER,
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};
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void cs35l56_reread_firmware_registers(struct device *dev, struct regmap *regmap)
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{
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int i;
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unsigned int val;
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for (i = 0; i < ARRAY_SIZE(cs35l56_firmware_registers); i++) {
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regmap_read(regmap, cs35l56_firmware_registers[i], &val);
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dev_dbg(dev, "%s: %d: %#x: %#x\n", __func__,
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i, cs35l56_firmware_registers[i], val);
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}
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}
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EXPORT_SYMBOL_NS_GPL(cs35l56_reread_firmware_registers, SND_SOC_CS35L56_SHARED);
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const struct cs_dsp_region cs35l56_dsp1_regions[] = {
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{ .type = WMFW_HALO_PM_PACKED, .base = CS35L56_DSP1_PMEM_0 },
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{ .type = WMFW_HALO_XM_PACKED, .base = CS35L56_DSP1_XMEM_PACKED_0 },
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{ .type = WMFW_HALO_YM_PACKED, .base = CS35L56_DSP1_YMEM_PACKED_0 },
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{ .type = WMFW_ADSP2_XM, .base = CS35L56_DSP1_XMEM_UNPACKED24_0 },
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{ .type = WMFW_ADSP2_YM, .base = CS35L56_DSP1_YMEM_UNPACKED24_0 },
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};
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EXPORT_SYMBOL_NS_GPL(cs35l56_dsp1_regions, SND_SOC_CS35L56_SHARED);
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static const u32 cs35l56_bclk_valid_for_pll_freq_table[] = {
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[0x0C] = 128000,
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[0x0F] = 256000,
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[0x11] = 384000,
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[0x12] = 512000,
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[0x15] = 768000,
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[0x17] = 1024000,
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[0x1A] = 1500000,
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[0x1B] = 1536000,
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[0x1C] = 2000000,
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[0x1D] = 2048000,
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[0x1E] = 2400000,
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[0x20] = 3000000,
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[0x21] = 3072000,
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[0x23] = 4000000,
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[0x24] = 4096000,
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[0x25] = 4800000,
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[0x27] = 6000000,
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[0x28] = 6144000,
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[0x29] = 6250000,
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[0x2A] = 6400000,
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[0x2E] = 8000000,
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[0x2F] = 8192000,
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[0x30] = 9600000,
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[0x32] = 12000000,
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[0x33] = 12288000,
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[0x37] = 13500000,
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[0x38] = 19200000,
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[0x39] = 22579200,
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[0x3B] = 24576000,
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};
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int cs35l56_get_bclk_freq_id(unsigned int freq)
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{
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int i;
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if (freq == 0)
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return -EINVAL;
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/* The BCLK frequency must be a valid PLL REFCLK */
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for (i = 0; i < ARRAY_SIZE(cs35l56_bclk_valid_for_pll_freq_table); ++i) {
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if (cs35l56_bclk_valid_for_pll_freq_table[i] == freq)
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return i;
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}
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return -EINVAL;
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}
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EXPORT_SYMBOL_NS_GPL(cs35l56_get_bclk_freq_id, SND_SOC_CS35L56_SHARED);
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static const char * const cs35l56_supplies[/* auto-sized */] = {
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"VDD_P",
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"VDD_IO",
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"VDD_A",
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};
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void cs35l56_fill_supply_names(struct regulator_bulk_data *data)
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{
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int i;
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BUILD_BUG_ON(ARRAY_SIZE(cs35l56_supplies) != CS35L56_NUM_BULK_SUPPLIES);
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for (i = 0; i < ARRAY_SIZE(cs35l56_supplies); i++)
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data[i].supply = cs35l56_supplies[i];
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}
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EXPORT_SYMBOL_NS_GPL(cs35l56_fill_supply_names, SND_SOC_CS35L56_SHARED);
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const char * const cs35l56_tx_input_texts[] = {
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"None", "ASP1RX1", "ASP1RX2", "VMON", "IMON", "ERRVOL", "CLASSH",
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"VDDBMON", "VBSTMON", "DSP1TX1", "DSP1TX2", "DSP1TX3", "DSP1TX4",
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"DSP1TX5", "DSP1TX6", "DSP1TX7", "DSP1TX8", "TEMPMON",
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"INTERPOLATOR", "SDW1RX1", "SDW1RX2",
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};
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EXPORT_SYMBOL_NS_GPL(cs35l56_tx_input_texts, SND_SOC_CS35L56_SHARED);
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const unsigned int cs35l56_tx_input_values[] = {
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CS35L56_INPUT_SRC_NONE,
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CS35L56_INPUT_SRC_ASP1RX1,
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CS35L56_INPUT_SRC_ASP1RX2,
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CS35L56_INPUT_SRC_VMON,
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CS35L56_INPUT_SRC_IMON,
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CS35L56_INPUT_SRC_ERR_VOL,
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CS35L56_INPUT_SRC_CLASSH,
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CS35L56_INPUT_SRC_VDDBMON,
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CS35L56_INPUT_SRC_VBSTMON,
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CS35L56_INPUT_SRC_DSP1TX1,
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CS35L56_INPUT_SRC_DSP1TX2,
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CS35L56_INPUT_SRC_DSP1TX3,
|
||
|
|
CS35L56_INPUT_SRC_DSP1TX4,
|
||
|
|
CS35L56_INPUT_SRC_DSP1TX5,
|
||
|
|
CS35L56_INPUT_SRC_DSP1TX6,
|
||
|
|
CS35L56_INPUT_SRC_DSP1TX7,
|
||
|
|
CS35L56_INPUT_SRC_DSP1TX8,
|
||
|
|
CS35L56_INPUT_SRC_TEMPMON,
|
||
|
|
CS35L56_INPUT_SRC_INTERPOLATOR,
|
||
|
|
CS35L56_INPUT_SRC_SWIRE_DP1_CHANNEL1,
|
||
|
|
CS35L56_INPUT_SRC_SWIRE_DP1_CHANNEL2,
|
||
|
|
};
|
||
|
|
EXPORT_SYMBOL_NS_GPL(cs35l56_tx_input_values, SND_SOC_CS35L56_SHARED);
|
||
|
|
|
||
|
|
struct regmap_config cs35l56_regmap_i2c = {
|
||
|
|
.reg_bits = 32,
|
||
|
|
.val_bits = 32,
|
||
|
|
.reg_stride = 4,
|
||
|
|
.reg_format_endian = REGMAP_ENDIAN_BIG,
|
||
|
|
.val_format_endian = REGMAP_ENDIAN_BIG,
|
||
|
|
.max_register = CS35L56_DSP1_PMEM_5114,
|
||
|
|
.reg_defaults = cs35l56_reg_defaults,
|
||
|
|
.num_reg_defaults = ARRAY_SIZE(cs35l56_reg_defaults),
|
||
|
|
.volatile_reg = cs35l56_volatile_reg,
|
||
|
|
.readable_reg = cs35l56_readable_reg,
|
||
|
|
.precious_reg = cs35l56_precious_reg,
|
||
|
|
.cache_type = REGCACHE_RBTREE,
|
||
|
|
};
|
||
|
|
EXPORT_SYMBOL_NS_GPL(cs35l56_regmap_i2c, SND_SOC_CS35L56_SHARED);
|
||
|
|
|
||
|
|
struct regmap_config cs35l56_regmap_spi = {
|
||
|
|
.reg_bits = 32,
|
||
|
|
.val_bits = 32,
|
||
|
|
.pad_bits = 16,
|
||
|
|
.reg_stride = 4,
|
||
|
|
.reg_format_endian = REGMAP_ENDIAN_BIG,
|
||
|
|
.val_format_endian = REGMAP_ENDIAN_BIG,
|
||
|
|
.max_register = CS35L56_DSP1_PMEM_5114,
|
||
|
|
.reg_defaults = cs35l56_reg_defaults,
|
||
|
|
.num_reg_defaults = ARRAY_SIZE(cs35l56_reg_defaults),
|
||
|
|
.volatile_reg = cs35l56_volatile_reg,
|
||
|
|
.readable_reg = cs35l56_readable_reg,
|
||
|
|
.precious_reg = cs35l56_precious_reg,
|
||
|
|
.cache_type = REGCACHE_RBTREE,
|
||
|
|
};
|
||
|
|
EXPORT_SYMBOL_NS_GPL(cs35l56_regmap_spi, SND_SOC_CS35L56_SHARED);
|
||
|
|
|
||
|
|
struct regmap_config cs35l56_regmap_sdw = {
|
||
|
|
.reg_bits = 32,
|
||
|
|
.val_bits = 32,
|
||
|
|
.reg_stride = 4,
|
||
|
|
.reg_format_endian = REGMAP_ENDIAN_LITTLE,
|
||
|
|
.val_format_endian = REGMAP_ENDIAN_BIG,
|
||
|
|
.max_register = CS35L56_DSP1_PMEM_5114,
|
||
|
|
.reg_defaults = cs35l56_reg_defaults,
|
||
|
|
.num_reg_defaults = ARRAY_SIZE(cs35l56_reg_defaults),
|
||
|
|
.volatile_reg = cs35l56_volatile_reg,
|
||
|
|
.readable_reg = cs35l56_readable_reg,
|
||
|
|
.precious_reg = cs35l56_precious_reg,
|
||
|
|
.cache_type = REGCACHE_RBTREE,
|
||
|
|
};
|
||
|
|
EXPORT_SYMBOL_NS_GPL(cs35l56_regmap_sdw, SND_SOC_CS35L56_SHARED);
|
||
|
|
|
||
|
|
MODULE_DESCRIPTION("ASoC CS35L56 Shared");
|
||
|
|
MODULE_AUTHOR("Richard Fitzgerald <rf@opensource.cirrus.com>");
|
||
|
|
MODULE_AUTHOR("Simon Trimmer <simont@opensource.cirrus.com>");
|
||
|
|
MODULE_LICENSE("GPL");
|