2023-08-30 17:31:07 +02:00
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// SPDX-License-Identifier: (GPL-2.0-only OR BSD-3-Clause)
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//
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// This file is provided under a dual BSD/GPLv2 license. When using or
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// redistributing this file, you may do so under either license.
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//
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// Copyright(c) 2022 Advanced Micro Devices, Inc.
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//
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// Authors: Ajit Kumar Pandey <AjitKumar.Pandey@amd.com>
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// V sujith kumar Reddy <Vsujithkumar.Reddy@amd.com>
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/* ACP-specific Common code */
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#include "../sof-priv.h"
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#include "../sof-audio.h"
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#include "../ops.h"
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#include "../sof-audio.h"
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#include "acp.h"
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#include "acp-dsp-offset.h"
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#include <sound/sof/xtensa.h>
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/**
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* amd_sof_ipc_dump() - This function is called when IPC tx times out.
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* @sdev: SOF device.
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*/
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void amd_sof_ipc_dump(struct snd_sof_dev *sdev)
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{
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const struct sof_amd_acp_desc *desc = get_chip_info(sdev->pdata);
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u32 base = desc->dsp_intr_base;
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u32 dsp_msg_write = sdev->debug_box.offset +
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offsetof(struct scratch_ipc_conf, sof_dsp_msg_write);
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u32 dsp_ack_write = sdev->debug_box.offset +
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offsetof(struct scratch_ipc_conf, sof_dsp_ack_write);
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u32 host_msg_write = sdev->debug_box.offset +
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offsetof(struct scratch_ipc_conf, sof_host_msg_write);
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u32 host_ack_write = sdev->debug_box.offset +
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offsetof(struct scratch_ipc_conf, sof_host_ack_write);
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u32 dsp_msg, dsp_ack, host_msg, host_ack, irq_stat;
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dsp_msg = snd_sof_dsp_read(sdev, ACP_DSP_BAR, ACP_SCRATCH_REG_0 + dsp_msg_write);
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dsp_ack = snd_sof_dsp_read(sdev, ACP_DSP_BAR, ACP_SCRATCH_REG_0 + dsp_ack_write);
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host_msg = snd_sof_dsp_read(sdev, ACP_DSP_BAR, ACP_SCRATCH_REG_0 + host_msg_write);
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host_ack = snd_sof_dsp_read(sdev, ACP_DSP_BAR, ACP_SCRATCH_REG_0 + host_ack_write);
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irq_stat = snd_sof_dsp_read(sdev, ACP_DSP_BAR, base + DSP_SW_INTR_STAT_OFFSET);
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dev_err(sdev->dev,
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"dsp_msg = %#x dsp_ack = %#x host_msg = %#x host_ack = %#x irq_stat = %#x\n",
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dsp_msg, dsp_ack, host_msg, host_ack, irq_stat);
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}
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/**
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* amd_get_registers() - This function is called in case of DSP oops
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* in order to gather information about the registers, filename and
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* linenumber and stack.
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* @sdev: SOF device.
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* @xoops: Stores information about registers.
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* @panic_info: Stores information about filename and line number.
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* @stack: Stores the stack dump.
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* @stack_words: Size of the stack dump.
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*/
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static void amd_get_registers(struct snd_sof_dev *sdev,
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struct sof_ipc_dsp_oops_xtensa *xoops,
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struct sof_ipc_panic_info *panic_info,
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u32 *stack, size_t stack_words)
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{
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u32 offset = sdev->dsp_oops_offset;
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/* first read registers */
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acp_mailbox_read(sdev, offset, xoops, sizeof(*xoops));
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/* then get panic info */
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if (xoops->arch_hdr.totalsize > EXCEPT_MAX_HDR_SIZE) {
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dev_err(sdev->dev, "invalid header size 0x%x. FW oops is bogus\n",
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xoops->arch_hdr.totalsize);
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return;
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}
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offset += xoops->arch_hdr.totalsize;
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acp_mailbox_read(sdev, offset, panic_info, sizeof(*panic_info));
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/* then get the stack */
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offset += sizeof(*panic_info);
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acp_mailbox_read(sdev, offset, stack, stack_words * sizeof(u32));
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}
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/**
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* amd_sof_dump() - This function is called when a panic message is
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* received from the firmware.
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* @sdev: SOF device.
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* @flags: parameter not used but required by ops prototype
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*/
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void amd_sof_dump(struct snd_sof_dev *sdev, u32 flags)
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{
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struct sof_ipc_dsp_oops_xtensa xoops;
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struct sof_ipc_panic_info panic_info;
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u32 stack[AMD_STACK_DUMP_SIZE];
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u32 status;
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/* Get information about the panic status from the debug box area.
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* Compute the trace point based on the status.
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*/
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if (sdev->dsp_oops_offset > sdev->debug_box.offset) {
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acp_mailbox_read(sdev, sdev->debug_box.offset, &status, sizeof(u32));
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} else {
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/* Read DSP Panic status from dsp_box.
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* As window information for exception box offset and size is not available
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* before FW_READY
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*/
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acp_mailbox_read(sdev, sdev->dsp_box.offset, &status, sizeof(u32));
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sdev->dsp_oops_offset = sdev->dsp_box.offset + sizeof(status);
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}
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/* Get information about the registers, the filename and line
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* number and the stack.
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*/
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amd_get_registers(sdev, &xoops, &panic_info, stack, AMD_STACK_DUMP_SIZE);
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/* Print the information to the console */
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sof_print_oops_and_stack(sdev, KERN_ERR, status, status, &xoops,
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&panic_info, stack, AMD_STACK_DUMP_SIZE);
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}
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struct snd_soc_acpi_mach *amd_sof_machine_select(struct snd_sof_dev *sdev)
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{
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struct snd_sof_pdata *sof_pdata = sdev->pdata;
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const struct sof_dev_desc *desc = sof_pdata->desc;
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struct snd_soc_acpi_mach *mach;
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mach = snd_soc_acpi_find_machine(desc->machines);
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if (!mach) {
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dev_warn(sdev->dev, "No matching ASoC machine driver found\n");
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return NULL;
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}
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sof_pdata->tplg_filename = mach->sof_tplg_filename;
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sof_pdata->fw_filename = mach->fw_filename;
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return mach;
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}
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/* AMD Common DSP ops */
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struct snd_sof_dsp_ops sof_acp_common_ops = {
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/* probe and remove */
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.probe = amd_sof_acp_probe,
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.remove = amd_sof_acp_remove,
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/* Register IO */
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.write = sof_io_write,
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.read = sof_io_read,
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/* Block IO */
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.block_read = acp_dsp_block_read,
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.block_write = acp_dsp_block_write,
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/*Firmware loading */
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.load_firmware = snd_sof_load_firmware_memcpy,
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.pre_fw_run = acp_dsp_pre_fw_run,
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.get_bar_index = acp_get_bar_index,
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/* DSP core boot */
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.run = acp_sof_dsp_run,
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/*IPC */
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.send_msg = acp_sof_ipc_send_msg,
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.ipc_msg_data = acp_sof_ipc_msg_data,
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.set_stream_data_offset = acp_set_stream_data_offset,
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.get_mailbox_offset = acp_sof_ipc_get_mailbox_offset,
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.get_window_offset = acp_sof_ipc_get_window_offset,
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.irq_thread = acp_sof_ipc_irq_thread,
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/* stream callbacks */
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.pcm_open = acp_pcm_open,
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.pcm_close = acp_pcm_close,
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.pcm_hw_params = acp_pcm_hw_params,
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2023-10-24 12:59:35 +02:00
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.pcm_pointer = acp_pcm_pointer,
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2023-08-30 17:31:07 +02:00
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.hw_info = SNDRV_PCM_INFO_MMAP |
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SNDRV_PCM_INFO_MMAP_VALID |
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SNDRV_PCM_INFO_INTERLEAVED |
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SNDRV_PCM_INFO_PAUSE |
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SNDRV_PCM_INFO_NO_PERIOD_WAKEUP,
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/* Machine driver callbacks */
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.machine_select = amd_sof_machine_select,
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.machine_register = sof_machine_register,
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.machine_unregister = sof_machine_unregister,
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/* Trace Logger */
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.trace_init = acp_sof_trace_init,
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.trace_release = acp_sof_trace_release,
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/* PM */
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.suspend = amd_sof_acp_suspend,
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.resume = amd_sof_acp_resume,
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.ipc_dump = amd_sof_ipc_dump,
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.dbg_dump = amd_sof_dump,
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.debugfs_add_region_item = snd_sof_debugfs_add_region_item_iomem,
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.dsp_arch_ops = &sof_xtensa_arch_ops,
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};
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EXPORT_SYMBOL_NS(sof_acp_common_ops, SND_SOC_SOF_AMD_COMMON);
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MODULE_IMPORT_NS(SND_SOC_SOF_AMD_COMMON);
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MODULE_IMPORT_NS(SND_SOC_SOF_XTENSA);
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MODULE_DESCRIPTION("ACP SOF COMMON Driver");
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MODULE_LICENSE("Dual BSD/GPL");
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