101 lines
2.4 KiB
C
101 lines
2.4 KiB
C
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// SPDX-License-Identifier: (GPL-2.0-only OR BSD-3-Clause)
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//
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// Copyright(c) 2022 Mediatek Corporation. All rights reserved.
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//
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// Author: Allen-KH Cheng <allen-kh.cheng@mediatek.com>
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// Tinghan Shen <tinghan.shen@mediatek.com>
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//
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// Hardware interface for mt8186 DSP clock
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#include <linux/clk.h>
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#include <linux/io.h>
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#include "../../sof-audio.h"
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#include "../../ops.h"
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#include "../adsp_helper.h"
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#include "mt8186.h"
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#include "mt8186-clk.h"
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static const char *adsp_clks[ADSP_CLK_MAX] = {
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[CLK_TOP_AUDIODSP] = "audiodsp",
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[CLK_TOP_ADSP_BUS] = "adsp_bus",
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};
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int mt8186_adsp_init_clock(struct snd_sof_dev *sdev)
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{
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struct adsp_priv *priv = sdev->pdata->hw_pdata;
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struct device *dev = sdev->dev;
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int i;
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priv->clk = devm_kcalloc(dev, ADSP_CLK_MAX, sizeof(*priv->clk), GFP_KERNEL);
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if (!priv->clk)
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return -ENOMEM;
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for (i = 0; i < ADSP_CLK_MAX; i++) {
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priv->clk[i] = devm_clk_get(dev, adsp_clks[i]);
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if (IS_ERR(priv->clk[i]))
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return PTR_ERR(priv->clk[i]);
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}
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return 0;
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}
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static int adsp_enable_all_clock(struct snd_sof_dev *sdev)
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{
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struct adsp_priv *priv = sdev->pdata->hw_pdata;
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struct device *dev = sdev->dev;
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int ret;
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ret = clk_prepare_enable(priv->clk[CLK_TOP_AUDIODSP]);
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if (ret) {
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dev_err(dev, "%s clk_prepare_enable(audiodsp) fail %d\n",
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__func__, ret);
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return ret;
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}
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ret = clk_prepare_enable(priv->clk[CLK_TOP_ADSP_BUS]);
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if (ret) {
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dev_err(dev, "%s clk_prepare_enable(adsp_bus) fail %d\n",
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__func__, ret);
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clk_disable_unprepare(priv->clk[CLK_TOP_AUDIODSP]);
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return ret;
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}
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return 0;
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}
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static void adsp_disable_all_clock(struct snd_sof_dev *sdev)
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{
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struct adsp_priv *priv = sdev->pdata->hw_pdata;
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clk_disable_unprepare(priv->clk[CLK_TOP_ADSP_BUS]);
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clk_disable_unprepare(priv->clk[CLK_TOP_AUDIODSP]);
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}
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int mt8186_adsp_clock_on(struct snd_sof_dev *sdev)
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{
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struct device *dev = sdev->dev;
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int ret;
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ret = adsp_enable_all_clock(sdev);
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if (ret) {
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dev_err(dev, "failed to adsp_enable_clock: %d\n", ret);
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return ret;
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}
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snd_sof_dsp_write(sdev, DSP_REG_BAR, ADSP_CK_EN,
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UART_EN | DMA_EN | TIMER_EN | COREDBG_EN | CORE_CLK_EN);
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snd_sof_dsp_write(sdev, DSP_REG_BAR, ADSP_UART_CTRL,
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UART_BCLK_CG | UART_RSTN);
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return 0;
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}
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void mt8186_adsp_clock_off(struct snd_sof_dev *sdev)
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{
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snd_sof_dsp_write(sdev, DSP_REG_BAR, ADSP_CK_EN, 0);
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snd_sof_dsp_write(sdev, DSP_REG_BAR, ADSP_UART_CTRL, 0);
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adsp_disable_all_clock(sdev);
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}
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