"BriefDescription":"Cycles when dispatch was stalled while the instruction was fetched from the local L2 after suffering a branch mispredict."
},
{
"EventCode":"0x1003C",
"EventName":"PM_EXEC_STALL_DMISS_L2L3",
"BriefDescription":"Cycles in which the oldest instruction in the pipeline was waiting for a load miss to resolve from either the local L2 or local L3."
"BriefDescription":"Cycles in which the oldest instruction in the pipeline finished at dispatch and did not require execution in the LSU, BRU or VSU."
},
{
"EventCode":"0x1005A",
"EventName":"PM_FLUSH_MPRED",
"BriefDescription":"A flush occurred due to a mispredicted branch. Includes target and direction."
},
{
"EventCode":"0x1C05A",
"EventName":"PM_DERAT_MISS_2M",
"BriefDescription":"Data ERAT Miss (Data TLB Access) page size 2M. Implies radix translation. When MMCR1[16]=0 this event counts only DERAT reloads for demand misses. When MMCR1[16]=1 this event includes demand misses and prefetches."
"BriefDescription":"Cycles in which the next-to-complete (NTC) instruction is held at dispatch because of power management."
},
{
"EventCode":"0x1E050",
"EventName":"PM_DISP_STALL_HELD_STF_MAPPER_CYC",
"BriefDescription":"Cycles in which the next-to-complete (NTC) instruction is held at dispatch because the STF mapper/SRB was full. Includes GPR (count, link, tar), VSR, VMR, FPR."
},
{
"EventCode":"0x1E054",
"EventName":"PM_EXEC_STALL_DMISS_L21_L31",
"BriefDescription":"Cycles in which the oldest instruction in the pipeline was waiting for a load miss to resolve from another core's L2 or L3 on the same chip."
},
{
"EventCode":"0x1E056",
"EventName":"PM_EXEC_STALL_STORE_PIPE",
"BriefDescription":"Cycles in which the oldest instruction in the pipeline was executing in the store unit. This does not include cycles spent handling store misses, PTESYNC instructions or TLBIE instructions."
"BriefDescription":"Cycles in which the next-to-complete (NTC) instruction is held at dispatch due to Issue queue full. Includes issue queue and branch queue."
"BriefDescription":"Cycles in which the oldest instruction in the pipeline was executing in the Load Store Unit. This does not include simple fixed point instructions."
"BriefDescription":"Cycles in which the oldest instruction in the pipeline was waiting for a load miss to resolve from a source beyond the local L2 or local L3."
"BriefDescription":"Cycles in which the oldest instruction in the pipeline was a TLBIE instruction executing in the Load Store Unit."
},
{
"EventCode":"0x2E01E",
"EventName":"PM_EXEC_STALL_NTC_FLUSH",
"BriefDescription":"Cycles in which the oldest instruction in the pipeline was executing in any unit before it was flushed. Note that if the flush of the oldest instruction happens after finish, the cycles from dispatch to issue will be included in PM_DISP_STALL and the cycles from issue to finish will be included in PM_EXEC_STALL and its corresponding children. This event will also count cycles when the previous next-to-finish (NTF) instruction is still completing and the new NTF instruction is stalled at dispatch."
"BriefDescription":"Cycles in which the oldest instruction in the pipeline (NTC) finishes. Note that instructions can finish out of order, therefore not all the instructions that finish have a Next-to-complete status."
"BriefDescription":"Cycles when dispatch was stalled because of a flush that happened to an instruction(s) that was not yet next-to-complete (NTC). PM_EXEC_STALL_NTC_FLUSH only includes instructions that were flushed after becoming NTC."
"BriefDescription":"Cycles in which the oldest instruction in the pipeline was waiting to finish in one of the execution units (BRU, LSU, VSU). Only cycles between issue and finish are counted in this category."
"BriefDescription":"Cycles in which the next-to-complete (NTC) instruction is held at dispatch while waiting on the Scoreboard. This event combines VSCR and FPSCR together."
},
{
"EventCode":"0x3001A",
"EventName":"PM_LSU_ST2_FIN",
"BriefDescription":"LSU Finished an internal operation in ST2 port."
"BriefDescription":"Cycles in which the oldest instruction in the pipeline was a store whose cache line was not resident in the L1 and was waiting for allocation of the missing line into the L1."
"BriefDescription":"Cycles in which the oldest instruction in the pipeline was waiting for the non-speculative finish of either a STCX waiting for its result or a load waiting for non-critical sectors of data and ECC."
"BriefDescription":"Cycles in which the oldest instruction in the pipeline was waiting for a load miss to resolve from the local memory, local OpenCAPI cache, or local OpenCAPI memory."
"BriefDescription":"Cycles in which the oldest instruction in the pipeline was not allowed to complete because it was interrupted by ANY exception, which has to be serviced before the instruction can complete."
"BriefDescription":"Cycles in which the oldest instruction in the pipeline was waiting for a load miss to resolve from the local L2 or local L3, without a dispatch conflict."
},
{
"EventCode":"0x34056",
"EventName":"PM_EXEC_STALL_LOAD_FINISH",
"BriefDescription":"Cycles in which the oldest instruction in the pipeline was finishing a load after its data was reloaded from a data source beyond the local L1; cycles in which the LSU was processing an L1-hit; cycles in which the next-to-finish (NTF) instruction merged with another load in the LMQ; cycles in which the NTF instruction is waiting for a data reload for a load miss, but the data comes back with a non-NTF instruction."
},
{
"EventCode":"0x34058",
"EventName":"PM_DISP_STALL_BR_MPRED_ICMISS",
"BriefDescription":"Cycles when dispatch was stalled after a mispredicted branch resulted in an instruction cache miss."
},
{
"EventCode":"0x3D05C",
"EventName":"PM_DISP_STALL_HELD_RENAME_CYC",
"BriefDescription":"Cycles in which the next-to-complete (NTC) instruction is held at dispatch because the mapper/SRB was full. Includes GPR (count, link, tar), VSR, VMR, FPR and XVFC."
"BriefDescription":"LSU Finished an internal operation (up to 4 per cycle)."
},
{
"EventCode":"0x40004",
"EventName":"PM_FXU_ISSUE",
"BriefDescription":"A fixed point instruction was issued to the VSU."
},
{
"EventCode":"0x40008",
"EventName":"PM_NTC_ALL_FIN",
"BriefDescription":"Cycles in which both instructions in the ICT entry pair show as finished. These are the cycles between finish and completion for the oldest pair of instructions in the pipeline."
"BriefDescription":"Cycles when dispatch was stalled while the instruction was fetched from sources beyond the local L3 after suffering a mispredicted branch."
"BriefDescription":"Cycles in which the oldest instruction in the pipeline was waiting for a load miss to resolve from the local L2 or local L3, with a dispatch conflict."
"BriefDescription":"Cycles in which the oldest instruction in the pipeline was executing in the Branch unit."
},
{
"EventCode":"0x4D01A",
"EventName":"PM_CMPL_STALL_HWSYNC",
"BriefDescription":"Cycles in which the oldest instruction in the pipeline was a hwsync waiting for response from L2 before completing."
},
{
"EventCode":"0x4D01C",
"EventName":"PM_EXEC_STALL_TLBIEL",
"BriefDescription":"Cycles in which the oldest instruction in the pipeline was a TLBIEL instruction executing in the Load Store Unit. TLBIEL instructions have lower overhead than TLBIE instructions because they don't get set to the nest."
"BriefDescription":"Cycles in which the oldest instruction in the pipeline completed without an ntf_type pulse. The ntf_pulse was missed by the ISU because the next-to-finish (NTF) instruction finishes and completions came too close together."
},
{
"EventCode":"0x4E01A",
"EventName":"PM_DISP_STALL_HELD_CYC",
"BriefDescription":"Cycles in which the next-to-complete (NTC) instruction is held at dispatch for any reason."
"BriefDescription":"Cycles in which the next-to-complete (NTC) instruction is held at dispatch because of a synchronizing instruction that requires the ICT to be empty before dispatch."
