linux-zen-desktop/tools/perf/pmu-events/arch/x86/alderlake/other.json

[
    {
        "BriefDescription": "ASSISTS.HARDWARE",
        "EventCode": "0xc1",
        "EventName": "ASSISTS.HARDWARE",
        "SampleAfterValue": "100003",
        "UMask": "0x4",
        "Unit": "cpu_core"
    },
    {
        "BriefDescription": "ASSISTS.PAGE_FAULT",
        "EventCode": "0xc1",
        "EventName": "ASSISTS.PAGE_FAULT",
        "SampleAfterValue": "1000003",
        "UMask": "0x8",
        "Unit": "cpu_core"
    },
    {
        "BriefDescription": "CORE_POWER.LICENSE_1",
        "EventCode": "0x28",
        "EventName": "CORE_POWER.LICENSE_1",
        "SampleAfterValue": "200003",
        "UMask": "0x2",
        "Unit": "cpu_core"
    },
    {
        "BriefDescription": "CORE_POWER.LICENSE_2",
        "EventCode": "0x28",
        "EventName": "CORE_POWER.LICENSE_2",
        "SampleAfterValue": "200003",
        "UMask": "0x4",
        "Unit": "cpu_core"
    },
    {
        "BriefDescription": "CORE_POWER.LICENSE_3",
        "EventCode": "0x28",
        "EventName": "CORE_POWER.LICENSE_3",
        "SampleAfterValue": "200003",
        "UMask": "0x8",
        "Unit": "cpu_core"
    },
    {
        "BriefDescription": "Counts modified writebacks from L1 cache and L2 cache that have any type of response.",
        "EventCode": "0xB7",
        "EventName": "OCR.COREWB_M.ANY_RESPONSE",
        "MSRIndex": "0x1a6,0x1a7",
        "MSRValue": "0x10008",
        "SampleAfterValue": "100003",
        "UMask": "0x1",
        "Unit": "cpu_atom"
    },
    {
        "BriefDescription": "Counts demand data reads that have any type of response.",
        "EventCode": "0xB7",
        "EventName": "OCR.DEMAND_DATA_RD.ANY_RESPONSE",
        "MSRIndex": "0x1a6,0x1a7",
        "MSRValue": "0x10001",
        "SampleAfterValue": "100003",
        "UMask": "0x1",
        "Unit": "cpu_atom"
    },
    {
        "BriefDescription": "Counts demand data reads that have any type of response.",
        "EventCode": "0x2A,0x2B",
        "EventName": "OCR.DEMAND_DATA_RD.ANY_RESPONSE",
        "MSRIndex": "0x1a6,0x1a7",
        "MSRValue": "0x10001",
        "SampleAfterValue": "100003",
        "UMask": "0x1",
        "Unit": "cpu_core"
    },
    {
        "BriefDescription": "Counts demand data reads that were supplied by DRAM.",
        "EventCode": "0x2A,0x2B",
        "EventName": "OCR.DEMAND_DATA_RD.DRAM",
        "MSRIndex": "0x1a6,0x1a7",
        "MSRValue": "0x184000001",
        "SampleAfterValue": "100003",
        "UMask": "0x1",
        "Unit": "cpu_core"
    },
    {
        "BriefDescription": "Counts demand reads for ownership (RFO) and software prefetches for exclusive ownership (PREFETCHW) that have any type of response.",
        "EventCode": "0xB7",
        "EventName": "OCR.DEMAND_RFO.ANY_RESPONSE",
        "MSRIndex": "0x1a6,0x1a7",
        "MSRValue": "0x10002",
        "SampleAfterValue": "100003",
        "UMask": "0x1",
        "Unit": "cpu_atom"
    },
    {
        "BriefDescription": "Counts demand read for ownership (RFO) requests and software prefetches for exclusive ownership (PREFETCHW) that have any type of response.",
        "EventCode": "0x2A,0x2B",
        "EventName": "OCR.DEMAND_RFO.ANY_RESPONSE",
        "MSRIndex": "0x1a6,0x1a7",
        "MSRValue": "0x10002",
        "SampleAfterValue": "100003",
        "UMask": "0x1",
        "Unit": "cpu_core"
    },
    {
        "BriefDescription": "Counts streaming stores that have any type of response.",
        "EventCode": "0xB7",
        "EventName": "OCR.STREAMING_WR.ANY_RESPONSE",
        "MSRIndex": "0x1a6,0x1a7",
        "MSRValue": "0x10800",
        "SampleAfterValue": "100003",
        "UMask": "0x1",
        "Unit": "cpu_atom"
    },
    {
        "BriefDescription": "Counts streaming stores that have any type of response.",
        "EventCode": "0x2A,0x2B",
        "EventName": "OCR.STREAMING_WR.ANY_RESPONSE",
        "MSRIndex": "0x1a6,0x1a7",
        "MSRValue": "0x10800",
        "SampleAfterValue": "100003",
        "UMask": "0x1",
        "Unit": "cpu_core"
    },
    {
        "BriefDescription": "Cycles when Reservation Station (RS) is empty for the thread.",
        "EventCode": "0xa5",
        "EventName": "RS.EMPTY",
        "PublicDescription": "Counts cycles during which the reservation station (RS) is empty for this logical processor. This is usually caused when the front-end pipeline runs into starvation periods (e.g. branch mispredictions or i-cache misses)",
        "SampleAfterValue": "1000003",
        "UMask": "0x7",
        "Unit": "cpu_core"
    },
    {
        "BriefDescription": "Counts end of periods where the Reservation Station (RS) was empty.",
        "CounterMask": "1",
        "EdgeDetect": "1",
        "EventCode": "0xa5",
        "EventName": "RS.EMPTY_COUNT",
        "Invert": "1",
        "PublicDescription": "Counts end of periods where the Reservation Station (RS) was empty. Could be useful to closely sample on front-end latency issues (see the FRONTEND_RETIRED event of designated precise events)",
        "SampleAfterValue": "100003",
        "UMask": "0x7",
        "Unit": "cpu_core"
    },
    {
        "BriefDescription": "This event is deprecated. Refer to new event RS.EMPTY_COUNT",
        "CounterMask": "1",
        "Deprecated": "1",
        "EdgeDetect": "1",
        "EventCode": "0xa5",
        "EventName": "RS_EMPTY.COUNT",
        "Invert": "1",
        "SampleAfterValue": "100003",
        "UMask": "0x7",
        "Unit": "cpu_core"
    },
    {
        "BriefDescription": "This event is deprecated. Refer to new event RS.EMPTY",
        "Deprecated": "1",
        "EventCode": "0xa5",
        "EventName": "RS_EMPTY.CYCLES",
        "SampleAfterValue": "1000003",
        "UMask": "0x7",
        "Unit": "cpu_core"
    },
    {
        "BriefDescription": "Cycles the uncore cannot take further requests",
        "CounterMask": "1",
        "EventCode": "0x2d",
        "EventName": "XQ.FULL_CYCLES",
        "PublicDescription": "number of cycles when the thread is active and the uncore cannot take any further requests (for example prefetches, loads or stores initiated by the Core that miss the L2 cache).",
        "SampleAfterValue": "1000003",
        "UMask": "0x1",
        "Unit": "cpu_core"
    }
]