"BriefDescription":"Number of FP Computational Uops Executed this cycle. The number of FADD, FSUB, FCOM, FMULs, integer MULs and IMULs, FDIVs, FPREMs, FSQRTS, integer DIVs, and IDIVs. This event does not distinguish an FADD used in the middle of a transcendental flow from a s.",
"BriefDescription":"Number of GSSE memory assist for stores. GSSE microcode assist is being invoked whenever the hardware is unable to properly handle GSSE-256b operations.",
"EventCode":"0xC1",
"EventName":"OTHER_ASSISTS.AVX_STORE",
"SampleAfterValue":"100003",
"UMask":"0x8"
},
{
"BriefDescription":"Number of transitions from AVX-256 to legacy SSE when penalty applicable.",
"EventCode":"0xC1",
"EventName":"OTHER_ASSISTS.AVX_TO_SSE",
"SampleAfterValue":"100003",
"UMask":"0x10"
},
{
"BriefDescription":"Number of transitions from SSE to AVX-256 when penalty applicable.",
"EventCode":"0xC1",
"EventName":"OTHER_ASSISTS.SSE_TO_AVX",
"SampleAfterValue":"100003",
"UMask":"0x20"
},
{
"BriefDescription":"Number of AVX-256 Computational FP double precision uops issued this cycle.",
"EventCode":"0x11",
"EventName":"SIMD_FP_256.PACKED_DOUBLE",
"SampleAfterValue":"2000003",
"UMask":"0x2"
},
{
"BriefDescription":"Number of GSSE-256 Computational FP single precision uops issued this cycle.",