"BriefDescription":"This event counts executed load operations with all the following traits: 1. addressing of the format [base + offset], 2. the offset is between 1 and 2047, 3. the address specified in the base register is in one page and the address [base+offset] is in an.",
"EventCode":"0xB6",
"EventName":"AGU_BYPASS_CANCEL.COUNT",
"SampleAfterValue":"100003",
"UMask":"0x1"
},
{
"BriefDescription":"Divide operations executed.",
"CounterMask":"1",
"EdgeDetect":"1",
"EventCode":"0x14",
"EventName":"ARITH.FPU_DIV",
"PublicDescription":"This event counts the number of the divide operations executed.",
"SampleAfterValue":"100003",
"UMask":"0x1"
},
{
"BriefDescription":"Cycles when divider is busy executing divide operations.",
"EventCode":"0x14",
"EventName":"ARITH.FPU_DIV_ACTIVE",
"SampleAfterValue":"2000003",
"UMask":"0x1"
},
{
"BriefDescription":"Speculative and retired branches.",
"EventCode":"0x88",
"EventName":"BR_INST_EXEC.ALL_BRANCHES",
"SampleAfterValue":"200003",
"UMask":"0xff"
},
{
"BriefDescription":"Speculative and retired macro-conditional branches.",
"EventCode":"0x88",
"EventName":"BR_INST_EXEC.ALL_CONDITIONAL",
"SampleAfterValue":"200003",
"UMask":"0xc1"
},
{
"BriefDescription":"Speculative and retired macro-unconditional branches excluding calls and indirects.",
"EventCode":"0x88",
"EventName":"BR_INST_EXEC.ALL_DIRECT_JMP",
"SampleAfterValue":"200003",
"UMask":"0xc2"
},
{
"BriefDescription":"Speculative and retired direct near calls.",
"EventCode":"0x88",
"EventName":"BR_INST_EXEC.ALL_DIRECT_NEAR_CALL",
"SampleAfterValue":"200003",
"UMask":"0xd0"
},
{
"BriefDescription":"Speculative and retired indirect branches excluding calls and returns.",
"PublicDescription":"Counts speculatively miss-predicted indirect branches at execution time. Counts for indirect near CALL or JMP instructions (RET excluded).",
"BriefDescription":"Count XClk pulses when this thread is unhalted and the other thread is halted.",
"EventCode":"0x3C",
"EventName":"CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE",
"SampleAfterValue":"2000003",
"UMask":"0x2"
},
{
"BriefDescription":"Reference cycles when the core is not in halt state.",
"EventName":"CPU_CLK_UNHALTED.REF_TSC",
"PublicDescription":"This event counts the number of reference cycles when the core is not in a halt state. The core enters the halt state when it is running the HLT instruction or the MWAIT instruction. This event is not affected by core frequency changes (for example, P states, TM2 transitions) but has the same incrementing frequency as the time stamp counter. This event can approximate elapsed time while the core was not in a halt state. This event has a constant ratio with the CPU_CLK_UNHALTED.REF_XCLK event. It is counted on a dedicated fixed counter, leaving the four (eight when Hyperthreading is disabled) programmable counters available for other events.",
"SampleAfterValue":"2000003",
"UMask":"0x3"
},
{
"BriefDescription":"Reference cycles when the thread is unhalted (counts at 100 MHz rate).",
"EventCode":"0x3C",
"EventName":"CPU_CLK_UNHALTED.REF_XCLK",
"SampleAfterValue":"2000003",
"UMask":"0x1"
},
{
"AnyThread":"1",
"BriefDescription":"Reference cycles when the at least one thread on the physical core is unhalted (counts at 100 MHz rate).",
"EventCode":"0x3C",
"EventName":"CPU_CLK_UNHALTED.REF_XCLK_ANY",
"SampleAfterValue":"2000003",
"UMask":"0x1"
},
{
"BriefDescription":"Core cycles when the thread is not in halt state.",
"EventName":"CPU_CLK_UNHALTED.THREAD",
"PublicDescription":"This event counts the number of core cycles while the thread is not in a halt state. The thread enters the halt state when it is running the HLT instruction. This event is a component in many key event ratios. The core frequency may change from time to time due to transitions associated with Enhanced Intel SpeedStep Technology or TM2. For this reason this event may have a changing ratio with regards to time. When the core frequency is constant, this event can approximate elapsed time while the core was not in the halt state. It is counted on a dedicated fixed counter, leaving the four (eight when Hyperthreading is disabled) programmable counters available for other events.",
"SampleAfterValue":"2000003",
"UMask":"0x2"
},
{
"AnyThread":"1",
"BriefDescription":"Core cycles when at least one thread on the physical core is not in halt state.",
"EventName":"CPU_CLK_UNHALTED.THREAD_ANY",
"SampleAfterValue":"2000003",
"UMask":"0x2"
},
{
"BriefDescription":"Thread cycles when thread is not in halt state.",
"EventCode":"0x3C",
"EventName":"CPU_CLK_UNHALTED.THREAD_P",
"SampleAfterValue":"2000003"
},
{
"AnyThread":"1",
"BriefDescription":"Core cycles when at least one thread on the physical core is not in halt state.",
"EventCode":"0x3C",
"EventName":"CPU_CLK_UNHALTED.THREAD_P_ANY",
"SampleAfterValue":"2000003"
},
{
"BriefDescription":"Each cycle there was a miss-pending demand load this thread, increment by 1. Note this is in DCU and connected to Umask 1. Miss Pending demand load should be deduced by OR-ing increment bits of DCACHE_MISS_PEND.PENDING.",
"CounterMask":"2",
"EventCode":"0xA3",
"EventName":"CYCLE_ACTIVITY.CYCLES_L1D_PENDING",
"SampleAfterValue":"2000003",
"UMask":"0x2"
},
{
"BriefDescription":"Each cycle there was a MLC-miss pending demand load this thread (i.e. Non-completed valid SQ entry allocated for demand load and waiting for Uncore), increment by 1. Note this is in MLC and connected to Umask 0.",
"CounterMask":"1",
"EventCode":"0xA3",
"EventName":"CYCLE_ACTIVITY.CYCLES_L2_PENDING",
"SampleAfterValue":"2000003",
"UMask":"0x1"
},
{
"BriefDescription":"Each cycle there was no dispatch for this thread, increment by 1. Note this is connect to Umask 2. No dispatch can be deduced from the UOPS_EXECUTED event.",
"CounterMask":"4",
"EventCode":"0xA3",
"EventName":"CYCLE_ACTIVITY.CYCLES_NO_DISPATCH",
"SampleAfterValue":"2000003",
"UMask":"0x4"
},
{
"BriefDescription":"Each cycle there was a miss-pending demand load this thread and no uops dispatched, increment by 1. Note this is in DCU and connected to Umask 1 and 2. Miss Pending demand load should be deduced by OR-ing increment bits of DCACHE_MISS_PEND.PENDING.",
"CounterMask":"6",
"EventCode":"0xA3",
"EventName":"CYCLE_ACTIVITY.STALLS_L1D_PENDING",
"SampleAfterValue":"2000003",
"UMask":"0x6"
},
{
"BriefDescription":"Each cycle there was a MLC-miss pending demand load and no uops dispatched on this thread (i.e. Non-completed valid SQ entry allocated for demand load and waiting for Uncore), increment by 1. Note this is in MLC and connected to Umask 0 and 2.",
"CounterMask":"5",
"EventCode":"0xA3",
"EventName":"CYCLE_ACTIVITY.STALLS_L2_PENDING",
"SampleAfterValue":"2000003",
"UMask":"0x5"
},
{
"BriefDescription":"Stall cycles because IQ is full.",
"EventCode":"0x87",
"EventName":"ILD_STALL.IQ_FULL",
"SampleAfterValue":"2000003",
"UMask":"0x4"
},
{
"BriefDescription":"Stalls caused by changing prefix length of the instruction.",
"EventCode":"0x87",
"EventName":"ILD_STALL.LCP",
"SampleAfterValue":"2000003",
"UMask":"0x1"
},
{
"BriefDescription":"Instructions retired from execution.",
"EventName":"INST_RETIRED.ANY",
"PublicDescription":"This event counts the number of instructions retired from execution. For instructions that consist of multiple micro-ops, this event counts the retirement of the last micro-op of the instruction. Counting continues during hardware interrupts, traps, and inside interrupt handlers.",
"SampleAfterValue":"2000003",
"UMask":"0x1"
},
{
"BriefDescription":"Number of instructions retired. General Counter - architectural event.",
"BriefDescription":"Cycles when Resource Allocation Table (RAT) external stall is sent to Instruction Decode Queue (IDQ) for the thread.",
"EventCode":"0x0D",
"EventName":"INT_MISC.RAT_STALL_CYCLES",
"SampleAfterValue":"2000003",
"UMask":"0x40"
},
{
"BriefDescription":"Number of cycles waiting for the checkpoints in Resource Allocation Table (RAT) to be recovered after Nuke due to all other cases except JEClear (e.g. whenever a ucode assist is needed like SSE exception, memory disambiguation, etc...).",
"CounterMask":"1",
"EventCode":"0x0D",
"EventName":"INT_MISC.RECOVERY_CYCLES",
"SampleAfterValue":"2000003",
"UMask":"0x3"
},
{
"AnyThread":"1",
"BriefDescription":"Core cycles the allocator was stalled due to recovery from earlier clear event for any thread running on the physical core (e.g. misprediction or memory nuke).",
"CounterMask":"1",
"EventCode":"0x0D",
"EventName":"INT_MISC.RECOVERY_CYCLES_ANY",
"SampleAfterValue":"2000003",
"UMask":"0x3"
},
{
"BriefDescription":"Number of occurrences waiting for the checkpoints in Resource Allocation Table (RAT) to be recovered after Nuke due to all other cases except JEClear (e.g. whenever a ucode assist is needed like SSE exception, memory disambiguation, etc...).",
"CounterMask":"1",
"EdgeDetect":"1",
"EventCode":"0x0D",
"EventName":"INT_MISC.RECOVERY_STALLS_COUNT",
"SampleAfterValue":"2000003",
"UMask":"0x3"
},
{
"BriefDescription":"Number of cases where any load ends up with a valid block-code written to the load buffer (including blocks due to Memory Order Buffer (MOB), Data Cache Unit (DCU), TLB, but load has no DCU miss).",
"EventCode":"0x03",
"EventName":"LD_BLOCKS.ALL_BLOCK",
"SampleAfterValue":"100003",
"UMask":"0x10"
},
{
"BriefDescription":"Loads delayed due to SB blocks, preceding store operations with known addresses but unknown data.",
"EventCode":"0x03",
"EventName":"LD_BLOCKS.DATA_UNKNOWN",
"SampleAfterValue":"100003",
"UMask":"0x1"
},
{
"BriefDescription":"This event counts the number of times that split load operations are temporarily blocked because all resources for handling the split accesses are in use.",
"EventCode":"0x03",
"EventName":"LD_BLOCKS.NO_SR",
"SampleAfterValue":"100003",
"UMask":"0x8"
},
{
"BriefDescription":"Cases when loads get true Block-on-Store blocking code preventing store forwarding.",
"PublicDescription":"This event counts loads that followed a store to the same address, where the data could not be forwarded inside the pipeline from the store to the load. The most common reason why store forwarding would be blocked is when a load's address range overlaps with a preceding smaller uncompleted store. See the table of not supported store forwards in the Intel(R) 64 and IA-32 Architectures Optimization Reference Manual. The penalty for blocked store forwarding is that the load must wait for the store to complete before it can be issued.",
"BriefDescription":"False dependencies in MOB due to partial compare.",
"EventCode":"0x07",
"EventName":"LD_BLOCKS_PARTIAL.ADDRESS_ALIAS",
"PublicDescription":"Aliasing occurs when a load is issued after a store and their memory addresses are offset by 4K. This event counts the number of loads that aliased with a preceding store, resulting in an extended address check in the pipeline. The enhanced address check typically has a performance penalty of 5 cycles.",
"SampleAfterValue":"100003",
"UMask":"0x1"
},
{
"BriefDescription":"This event counts the number of times that load operations are temporarily blocked because of older stores, with addresses that are not yet known. A load operation may incur more than one block of this type.",
"EventCode":"0x07",
"EventName":"LD_BLOCKS_PARTIAL.ALL_STA_BLOCK",
"SampleAfterValue":"100003",
"UMask":"0x8"
},
{
"BriefDescription":"Not software-prefetch load dispatches that hit FB allocated for hardware prefetch.",
"EventCode":"0x4C",
"EventName":"LOAD_HIT_PRE.HW_PF",
"SampleAfterValue":"100003",
"UMask":"0x2"
},
{
"BriefDescription":"Not software-prefetch load dispatches that hit FB allocated for software prefetch.",
"EventCode":"0x4C",
"EventName":"LOAD_HIT_PRE.SW_PF",
"SampleAfterValue":"100003",
"UMask":"0x1"
},
{
"BriefDescription":"Cycles 4 Uops delivered by the LSD, but didn't come from the decoder.",
"CounterMask":"4",
"EventCode":"0xA8",
"EventName":"LSD.CYCLES_4_UOPS",
"SampleAfterValue":"2000003",
"UMask":"0x1"
},
{
"BriefDescription":"Cycles Uops delivered by the LSD, but didn't come from the decoder.",
"CounterMask":"1",
"EventCode":"0xA8",
"EventName":"LSD.CYCLES_ACTIVE",
"SampleAfterValue":"2000003",
"UMask":"0x1"
},
{
"BriefDescription":"Number of Uops delivered by the LSD.",
"EventCode":"0xA8",
"EventName":"LSD.UOPS",
"SampleAfterValue":"2000003",
"UMask":"0x1"
},
{
"BriefDescription":"Number of machine clears (nukes) of any type.",
"CounterMask":"1",
"EdgeDetect":"1",
"EventCode":"0xc3",
"EventName":"MACHINE_CLEARS.COUNT",
"SampleAfterValue":"100003",
"UMask":"0x1"
},
{
"BriefDescription":"This event counts the number of executed Intel AVX masked load operations that refer to an illegal address range with the mask bits set to 0.",
"EventCode":"0xC3",
"EventName":"MACHINE_CLEARS.MASKMOV",
"PublicDescription":"Maskmov false fault - counts number of time ucode passes through Maskmov flow due to instruction's mask being 0 while the flow was completed without raising a fault.",
"PublicDescription":"This event is incremented when self-modifying code (SMC) is detected, which causes a machine clear. Machine clears can have a significant performance impact if they are happening frequently.",
"PublicDescription":"This event counts the number of cycles spent executing performance-sensitive flags-merging uops. For example, shift CL (merge_arith_flags). For more details, See the Intel(R) 64 and IA-32 Architectures Optimization Reference Manual.",
"SampleAfterValue":"2000003",
"UMask":"0x20"
},
{
"BriefDescription":"Multiply packed/scalar single precision uops allocated.",
"EventCode":"0x59",
"EventName":"PARTIAL_RAT_STALLS.MUL_SINGLE_UOP",
"SampleAfterValue":"2000003",
"UMask":"0x80"
},
{
"BriefDescription":"Cycles with at least one slow LEA uop being allocated.",
"EventCode":"0x59",
"EventName":"PARTIAL_RAT_STALLS.SLOW_LEA_WINDOW",
"PublicDescription":"This event counts the number of cycles with at least one slow LEA uop being allocated. A uop is generally considered as slow LEA if it has three sources (for example, two sources and immediate) regardless of whether it is a result of LEA instruction or not. Examples of the slow LEA uop are or uops with base, index, and offset source operands using base and index reqisters, where base is EBR/RBP/R13, using RIP relative or 16-bit addressing modes. See the Intel(R) 64 and IA-32 Architectures Optimization Reference Manual for more details about slow LEA instructions.",
"BriefDescription":"Counts the cycles of stall due to lack of load buffers.",
"EventCode":"0xA2",
"EventName":"RESOURCE_STALLS.LB",
"SampleAfterValue":"2000003",
"UMask":"0x2"
},
{
"BriefDescription":"Resource stalls due to load or store buffers all being in use.",
"EventCode":"0xA2",
"EventName":"RESOURCE_STALLS.LB_SB",
"SampleAfterValue":"2000003",
"UMask":"0xa"
},
{
"BriefDescription":"Resource stalls due to memory buffers or Reservation Station (RS) being fully utilized.",
"EventCode":"0xA2",
"EventName":"RESOURCE_STALLS.MEM_RS",
"SampleAfterValue":"2000003",
"UMask":"0xe"
},
{
"BriefDescription":"Resource stalls due to Rob being full, FCSW, MXCSR and OTHER.",
"EventCode":"0xA2",
"EventName":"RESOURCE_STALLS.OOO_RSRC",
"SampleAfterValue":"2000003",
"UMask":"0xf0"
},
{
"BriefDescription":"Cycles stalled due to re-order buffer full.",
"EventCode":"0xA2",
"EventName":"RESOURCE_STALLS.ROB",
"SampleAfterValue":"2000003",
"UMask":"0x10"
},
{
"BriefDescription":"Cycles stalled due to no eligible RS entry available.",
"EventCode":"0xA2",
"EventName":"RESOURCE_STALLS.RS",
"SampleAfterValue":"2000003",
"UMask":"0x4"
},
{
"BriefDescription":"Cycles stalled due to no store buffers available. (not including draining form sync).",
"EventCode":"0xA2",
"EventName":"RESOURCE_STALLS.SB",
"SampleAfterValue":"2000003",
"UMask":"0x8"
},
{
"BriefDescription":"Cycles with either free list is empty.",
"EventCode":"0x5B",
"EventName":"RESOURCE_STALLS2.ALL_FL_EMPTY",
"SampleAfterValue":"2000003",
"UMask":"0xc"
},
{
"BriefDescription":"Resource stalls2 control structures full for physical registers.",
"EventCode":"0x5B",
"EventName":"RESOURCE_STALLS2.ALL_PRF_CONTROL",
"SampleAfterValue":"2000003",
"UMask":"0xf"
},
{
"BriefDescription":"Cycles when Allocator is stalled if BOB is full and new branch needs it.",
"EventCode":"0x5B",
"EventName":"RESOURCE_STALLS2.BOB_FULL",
"SampleAfterValue":"2000003",
"UMask":"0x40"
},
{
"BriefDescription":"Resource stalls out of order resources full.",
"EventCode":"0x5B",
"EventName":"RESOURCE_STALLS2.OOO_RSRC",
"SampleAfterValue":"2000003",
"UMask":"0x4f"
},
{
"BriefDescription":"Count cases of saving new LBR.",
"EventCode":"0xCC",
"EventName":"ROB_MISC_EVENTS.LBR_INSERTS",
"SampleAfterValue":"2000003",
"UMask":"0x20"
},
{
"BriefDescription":"Cycles when Reservation Station (RS) is empty for the thread.",
"EventCode":"0x5E",
"EventName":"RS_EVENTS.EMPTY_CYCLES",
"SampleAfterValue":"2000003",
"UMask":"0x1"
},
{
"BriefDescription":"Counts end of periods where the Reservation Station (RS) was empty. Could be useful to precisely locate Frontend Latency Bound issues.",
"CounterMask":"1",
"EdgeDetect":"1",
"EventCode":"0x5E",
"EventName":"RS_EVENTS.EMPTY_END",
"Invert":"1",
"SampleAfterValue":"2000003",
"UMask":"0x1"
},
{
"BriefDescription":"Uops dispatched from any thread.",
"EventCode":"0xB1",
"EventName":"UOPS_DISPATCHED.CORE",
"SampleAfterValue":"2000003",
"UMask":"0x2"
},
{
"BriefDescription":"Uops dispatched per thread.",
"EventCode":"0xB1",
"EventName":"UOPS_DISPATCHED.THREAD",
"SampleAfterValue":"2000003",
"UMask":"0x1"
},
{
"BriefDescription":"Cycles per thread when uops are dispatched to port 0.",
"EventCode":"0xA1",
"EventName":"UOPS_DISPATCHED_PORT.PORT_0",
"SampleAfterValue":"2000003",
"UMask":"0x1"
},
{
"AnyThread":"1",
"BriefDescription":"Cycles per core when uops are dispatched to port 0.",
"EventCode":"0xA1",
"EventName":"UOPS_DISPATCHED_PORT.PORT_0_CORE",
"SampleAfterValue":"2000003",
"UMask":"0x1"
},
{
"BriefDescription":"Cycles per thread when uops are dispatched to port 1.",
"EventCode":"0xA1",
"EventName":"UOPS_DISPATCHED_PORT.PORT_1",
"SampleAfterValue":"2000003",
"UMask":"0x2"
},
{
"AnyThread":"1",
"BriefDescription":"Cycles per core when uops are dispatched to port 1.",
"EventCode":"0xA1",
"EventName":"UOPS_DISPATCHED_PORT.PORT_1_CORE",
"SampleAfterValue":"2000003",
"UMask":"0x2"
},
{
"BriefDescription":"Cycles per thread when load or STA uops are dispatched to port 2.",
"EventCode":"0xA1",
"EventName":"UOPS_DISPATCHED_PORT.PORT_2",
"SampleAfterValue":"2000003",
"UMask":"0xc"
},
{
"AnyThread":"1",
"BriefDescription":"Cycles per core when load or STA uops are dispatched to port 2.",
"EventCode":"0xA1",
"EventName":"UOPS_DISPATCHED_PORT.PORT_2_CORE",
"SampleAfterValue":"2000003",
"UMask":"0xc"
},
{
"BriefDescription":"Cycles per thread when load or STA uops are dispatched to port 3.",
"EventCode":"0xA1",
"EventName":"UOPS_DISPATCHED_PORT.PORT_3",
"SampleAfterValue":"2000003",
"UMask":"0x30"
},
{
"AnyThread":"1",
"BriefDescription":"Cycles per core when load or STA uops are dispatched to port 3.",
"EventCode":"0xA1",
"EventName":"UOPS_DISPATCHED_PORT.PORT_3_CORE",
"SampleAfterValue":"2000003",
"UMask":"0x30"
},
{
"BriefDescription":"Cycles per thread when uops are dispatched to port 4.",
"EventCode":"0xA1",
"EventName":"UOPS_DISPATCHED_PORT.PORT_4",
"SampleAfterValue":"2000003",
"UMask":"0x40"
},
{
"AnyThread":"1",
"BriefDescription":"Cycles per core when uops are dispatched to port 4.",
"EventCode":"0xA1",
"EventName":"UOPS_DISPATCHED_PORT.PORT_4_CORE",
"SampleAfterValue":"2000003",
"UMask":"0x40"
},
{
"BriefDescription":"Cycles per thread when uops are dispatched to port 5.",
"EventCode":"0xA1",
"EventName":"UOPS_DISPATCHED_PORT.PORT_5",
"SampleAfterValue":"2000003",
"UMask":"0x80"
},
{
"AnyThread":"1",
"BriefDescription":"Cycles per core when uops are dispatched to port 5.",
"EventCode":"0xA1",
"EventName":"UOPS_DISPATCHED_PORT.PORT_5_CORE",
"SampleAfterValue":"2000003",
"UMask":"0x80"
},
{
"BriefDescription":"Cycles at least 1 micro-op is executed from any thread on physical core.",
"CounterMask":"1",
"EventCode":"0xB1",
"EventName":"UOPS_EXECUTED.CORE_CYCLES_GE_1",
"SampleAfterValue":"2000003",
"UMask":"0x2"
},
{
"BriefDescription":"Cycles at least 2 micro-op is executed from any thread on physical core.",
"CounterMask":"2",
"EventCode":"0xB1",
"EventName":"UOPS_EXECUTED.CORE_CYCLES_GE_2",
"SampleAfterValue":"2000003",
"UMask":"0x2"
},
{
"BriefDescription":"Cycles at least 3 micro-op is executed from any thread on physical core.",
"CounterMask":"3",
"EventCode":"0xB1",
"EventName":"UOPS_EXECUTED.CORE_CYCLES_GE_3",
"SampleAfterValue":"2000003",
"UMask":"0x2"
},
{
"BriefDescription":"Cycles at least 4 micro-op is executed from any thread on physical core.",
"CounterMask":"4",
"EventCode":"0xB1",
"EventName":"UOPS_EXECUTED.CORE_CYCLES_GE_4",
"SampleAfterValue":"2000003",
"UMask":"0x2"
},
{
"BriefDescription":"Cycles with no micro-ops executed from any thread on physical core.",
"EventCode":"0xB1",
"EventName":"UOPS_EXECUTED.CORE_CYCLES_NONE",
"Invert":"1",
"SampleAfterValue":"2000003",
"UMask":"0x2"
},
{
"BriefDescription":"Uops that Resource Allocation Table (RAT) issues to Reservation Station (RS).",
"EventCode":"0x0E",
"EventName":"UOPS_ISSUED.ANY",
"PublicDescription":"This event counts the number of Uops issued by the front-end of the pipeilne to the back-end.",
"SampleAfterValue":"2000003",
"UMask":"0x1"
},
{
"AnyThread":"1",
"BriefDescription":"Cycles when Resource Allocation Table (RAT) does not issue Uops to Reservation Station (RS) for all threads.",
"CounterMask":"1",
"EventCode":"0x0E",
"EventName":"UOPS_ISSUED.CORE_STALL_CYCLES",
"Invert":"1",
"SampleAfterValue":"2000003",
"UMask":"0x1"
},
{
"BriefDescription":"Cycles when Resource Allocation Table (RAT) does not issue Uops to Reservation Station (RS) for the thread.",
"PublicDescription":"This event counts the number of retirement slots used each cycle. There are potentially 4 slots that can be used each cycle - meaning, 4 micro-ops or 4 instructions could retire each cycle. This event is used in determining the 'Retiring' category of the Top-Down pipeline slots characterization. (Precise Event - PEBS)",
"SampleAfterValue":"2000003",
"UMask":"0x2"
},
{
"BriefDescription":"Cycles without actually retired uops.",
"CounterMask":"1",
"EventCode":"0xC2",
"EventName":"UOPS_RETIRED.STALL_CYCLES",
"Invert":"1",
"SampleAfterValue":"2000003",
"UMask":"0x1"
},
{
"BriefDescription":"Cycles with less than 10 actually retired uops.",
