133 lines
3.2 KiB
C
133 lines
3.2 KiB
C
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// SPDX-License-Identifier: GPL-2.0+
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#include <errno.h>
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#include <setjmp.h>
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#include <signal.h>
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#include <sys/types.h>
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#include <sys/wait.h>
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#include "dexcr.h"
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#include "reg.h"
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#include "utils.h"
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static jmp_buf generic_signal_jump_buf;
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static void generic_signal_handler(int signum, siginfo_t *info, void *context)
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{
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longjmp(generic_signal_jump_buf, 0);
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}
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bool dexcr_exists(void)
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{
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struct sigaction old;
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volatile bool exists;
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old = push_signal_handler(SIGILL, generic_signal_handler);
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if (setjmp(generic_signal_jump_buf))
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goto out;
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/*
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* If the SPR is not recognised by the hardware it triggers
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* a hypervisor emulation interrupt. If the kernel does not
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* recognise/try to emulate it, we receive a SIGILL signal.
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*
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* If we do not receive a signal, assume we have the SPR or the
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* kernel is trying to emulate it correctly.
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*/
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exists = false;
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mfspr(SPRN_DEXCR_RO);
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exists = true;
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out:
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pop_signal_handler(SIGILL, old);
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return exists;
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}
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/*
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* Just test if a bad hashchk triggers a signal, without checking
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* for support or if the NPHIE aspect is enabled.
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*/
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bool hashchk_triggers(void)
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{
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struct sigaction old;
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volatile bool triggers;
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old = push_signal_handler(SIGILL, generic_signal_handler);
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if (setjmp(generic_signal_jump_buf))
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goto out;
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triggers = true;
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do_bad_hashchk();
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triggers = false;
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out:
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pop_signal_handler(SIGILL, old);
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return triggers;
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}
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unsigned int get_dexcr(enum dexcr_source source)
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{
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switch (source) {
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case DEXCR:
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return mfspr(SPRN_DEXCR_RO);
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case HDEXCR:
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return mfspr(SPRN_HDEXCR_RO);
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case EFFECTIVE:
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return mfspr(SPRN_DEXCR_RO) | mfspr(SPRN_HDEXCR_RO);
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default:
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FAIL_IF_EXIT_MSG(true, "bad enum dexcr_source");
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}
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}
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void await_child_success(pid_t pid)
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{
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int wstatus;
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FAIL_IF_EXIT_MSG(pid == -1, "fork failed");
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FAIL_IF_EXIT_MSG(waitpid(pid, &wstatus, 0) == -1, "wait failed");
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FAIL_IF_EXIT_MSG(!WIFEXITED(wstatus), "child did not exit cleanly");
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FAIL_IF_EXIT_MSG(WEXITSTATUS(wstatus) != 0, "child exit error");
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}
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/*
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* Perform a hashst instruction. The following components determine the result
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*
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* 1. The LR value (any register technically)
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* 2. The SP value (also any register, but it must be a valid address)
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* 3. A secret key managed by the kernel
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*
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* The result is stored to the address held in SP.
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*/
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void hashst(unsigned long lr, void *sp)
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{
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asm volatile ("addi 31, %0, 0;" /* set r31 (pretend LR) to lr */
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"addi 30, %1, 8;" /* set r30 (pretend SP) to sp + 8 */
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PPC_RAW_HASHST(31, -8, 30) /* compute hash into stack location */
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: : "r" (lr), "r" (sp) : "r31", "r30", "memory");
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}
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/*
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* Perform a hashchk instruction. A hash is computed as per hashst(),
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* however the result is not stored to memory. Instead the existing
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* value is read and compared against the computed hash.
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*
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* If they match, execution continues.
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* If they differ, an interrupt triggers.
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*/
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void hashchk(unsigned long lr, void *sp)
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{
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asm volatile ("addi 31, %0, 0;" /* set r31 (pretend LR) to lr */
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"addi 30, %1, 8;" /* set r30 (pretend SP) to sp + 8 */
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PPC_RAW_HASHCHK(31, -8, 30) /* check hash at stack location */
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: : "r" (lr), "r" (sp) : "r31", "r30", "memory");
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}
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void do_bad_hashchk(void)
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{
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unsigned long hash = 0;
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hashst(0, &hash);
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hash += 1;
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hashchk(0, &hash);
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}
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