98 lines
3.3 KiB
YAML
98 lines
3.3 KiB
YAML
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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
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%YAML 1.2
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---
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$id: "http://devicetree.org/schemas/arm/tegra/nvidia,tegra194-cbb.yaml#"
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$schema: "http://devicetree.org/meta-schemas/core.yaml#"
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title: NVIDIA Tegra194 CBB 1.0
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maintainers:
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- Sumit Gupta <sumitg@nvidia.com>
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description: |+
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The Control Backbone (CBB) is comprised of the physical path from an
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initiator to a target's register configuration space. CBB 1.0 has
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multiple hierarchical sub-NOCs (Network-on-Chip) and connects various
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initiators and targets using different bridges like AXIP2P, AXI2APB.
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This driver handles errors due to illegal register accesses reported
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by the NOCs inside the CBB. NOCs reporting errors are cluster NOCs
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"AON-NOC, SCE-NOC, RCE-NOC, BPMP-NOC, CV-NOC" and "CBB Central NOC"
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which is the main NOC.
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By default, the access issuing initiator is informed about the error
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using SError or Data Abort exception unless the ERD (Error Response
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Disable) is enabled/set for that initiator. If the ERD is enabled, then
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SError or Data Abort is masked and the error is reported with interrupt.
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- For CCPLEX (CPU Complex) initiator, the driver sets ERD bit. So, the
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errors due to illegal accesses from CCPLEX are reported by interrupts.
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If ERD is not set, then error is reported by SError.
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- For other initiators, the ERD is disabled. So, the access issuing
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initiator is informed about the illegal access by Data Abort exception.
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In addition, an interrupt is also generated to CCPLEX. These initiators
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include all engines using Cortex-R5 (which is ARMv7 CPU cluster) and
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engines like TSEC (Security co-processor), NVDEC (NVIDIA Video Decoder
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engine) etc which can initiate transactions.
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The driver prints relevant debug information like Error Code, Error
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Description, Master, Address, AXI ID, Cache, Protection, Security Group
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etc on receiving error notification.
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properties:
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$nodename:
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pattern: "^[a-z]+-noc@[0-9a-f]+$"
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compatible:
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enum:
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- nvidia,tegra194-cbb-noc
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- nvidia,tegra194-aon-noc
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- nvidia,tegra194-bpmp-noc
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- nvidia,tegra194-rce-noc
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- nvidia,tegra194-sce-noc
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reg:
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maxItems: 1
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interrupts:
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description:
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CCPLEX receives secure or nonsecure interrupt depending on error type.
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A secure interrupt is received for SEC(firewall) & SLV errors and a
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non-secure interrupt is received for TMO & DEC errors.
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items:
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- description: non-secure interrupt
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- description: secure interrupt
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nvidia,axi2apb:
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$ref: '/schemas/types.yaml#/definitions/phandle'
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description:
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Specifies the node having all axi2apb bridges which need to be checked
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for any error logged in their status register.
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nvidia,apbmisc:
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$ref: '/schemas/types.yaml#/definitions/phandle'
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description:
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Specifies the apbmisc node which need to be used for reading the ERD
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register.
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additionalProperties: false
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required:
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- compatible
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- reg
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- interrupts
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- nvidia,apbmisc
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examples:
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- |
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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cbb-noc@2300000 {
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compatible = "nvidia,tegra194-cbb-noc";
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reg = <0x02300000 0x1000>;
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interrupts = <GIC_SPI 230 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 231 IRQ_TYPE_LEVEL_HIGH>;
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nvidia,axi2apb = <&axi2apb>;
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nvidia,apbmisc = <&apbmisc>;
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};
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