108 lines
2.5 KiB
YAML
108 lines
2.5 KiB
YAML
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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
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# Copyright (C) 2020 BAIKAL ELECTRONICS, JSC
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/bus/baikal,bt1-axi.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: Baikal-T1 AXI-bus
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maintainers:
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- Serge Semin <fancer.lancer@gmail.com>
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description: |
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AXI3-bus is the main communication bus of Baikal-T1 SoC connecting all
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high-speed peripheral IP-cores with RAM controller and with MIPS P5600
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cores. Traffic arbitration is done by means of DW AXI Interconnect (so
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called AXI Main Interconnect) routing IO requests from one block to
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another: from CPU to SoC peripherals and between some SoC peripherals
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(mostly between peripheral devices and RAM, but also between DMA and
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some peripherals). In case of any protocol error, device not responding
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an IRQ is raised and a faulty situation is reported to the AXI EHB
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(Errors Handler Block) embedded on top of the DW AXI Interconnect and
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accessible by means of the Baikal-T1 System Controller.
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allOf:
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- $ref: /schemas/simple-bus.yaml#
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properties:
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compatible:
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contains:
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const: baikal,bt1-axi
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reg:
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minItems: 1
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items:
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- description: Synopsys DesignWare AXI Interconnect QoS registers
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- description: AXI EHB MMIO system controller registers
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reg-names:
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minItems: 1
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items:
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- const: qos
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- const: ehb
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'#interconnect-cells':
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const: 1
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syscon:
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$ref: /schemas/types.yaml#/definitions/phandle
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description: Phandle to the Baikal-T1 System Controller DT node
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interrupts:
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maxItems: 1
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clocks:
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items:
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- description: Main Interconnect uplink reference clock
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clock-names:
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items:
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- const: aclk
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resets:
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items:
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- description: Main Interconnect reset line
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reset-names:
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items:
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- const: arst
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unevaluatedProperties: false
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required:
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- compatible
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- reg
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- reg-names
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- syscon
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- interrupts
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- clocks
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- clock-names
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examples:
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- |
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#include <dt-bindings/interrupt-controller/mips-gic.h>
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bus@1f05a000 {
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compatible = "baikal,bt1-axi", "simple-bus";
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reg = <0x1f05a000 0x1000>,
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<0x1f04d110 0x8>;
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reg-names = "qos", "ehb";
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#address-cells = <1>;
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#size-cells = <1>;
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#interconnect-cells = <1>;
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syscon = <&syscon>;
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ranges;
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interrupts = <GIC_SHARED 127 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&ccu_axi 0>;
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clock-names = "aclk";
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resets = <&ccu_axi 0>;
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reset-names = "arst";
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};
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...
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