63 lines
1.6 KiB
YAML
63 lines
1.6 KiB
YAML
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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/clock/qcom,sm8550-gcc.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: Qualcomm Global Clock & Reset Controller on SM8550
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maintainers:
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- Bjorn Andersson <andersson@kernel.org>
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description: |
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Qualcomm global clock control module provides the clocks, resets and power
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domains on SM8550
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See also:: include/dt-bindings/clock/qcom,sm8550-gcc.h
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properties:
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compatible:
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const: qcom,sm8550-gcc
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clocks:
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items:
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- description: Board XO source
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- description: Sleep clock source
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- description: PCIE 0 Pipe clock source
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- description: PCIE 1 Pipe clock source
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- description: PCIE 1 Phy Auxiliary clock source
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- description: UFS Phy Rx symbol 0 clock source
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- description: UFS Phy Rx symbol 1 clock source
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- description: UFS Phy Tx symbol 0 clock source
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- description: USB3 Phy wrapper pipe clock source
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required:
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- compatible
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- clocks
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allOf:
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- $ref: qcom,gcc.yaml#
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unevaluatedProperties: false
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examples:
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- |
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#include <dt-bindings/clock/qcom,rpmh.h>
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clock-controller@100000 {
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compatible = "qcom,sm8550-gcc";
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reg = <0x00100000 0x001f4200>;
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clocks = <&rpmhcc RPMH_CXO_CLK>, <&sleep_clk>,
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<&pcie0_phy>,
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<&pcie1_phy>,
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<&pcie_1_phy_aux_clk>,
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<&ufs_mem_phy 0>,
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<&ufs_mem_phy 1>,
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<&ufs_mem_phy 2>,
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<&usb_1_qmpphy>;
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#clock-cells = <1>;
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#reset-cells = <1>;
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#power-domain-cells = <1>;
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};
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...
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