54 lines
1.4 KiB
YAML
54 lines
1.4 KiB
YAML
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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/display/bridge/synopsys,dw-hdmi.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: Common Properties for Synopsys DesignWare HDMI TX Controller
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maintainers:
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- Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
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description: |
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This document defines device tree properties for the Synopsys DesignWare HDMI
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TX controller (DWC HDMI TX) IP core. It doesn't constitute a full device tree
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binding specification by itself but is meant to be referenced by device tree
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bindings for the platform-specific integrations of the DWC HDMI TX.
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When referenced from platform device tree bindings the properties defined in
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this document are defined as follows. The platform device tree bindings are
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responsible for defining whether each property is required or optional.
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properties:
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reg:
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maxItems: 1
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reg-io-width:
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description:
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Width (in bytes) of the registers specified by the reg property.
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enum: [1, 4]
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default: 1
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clocks:
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minItems: 2
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maxItems: 5
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items:
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- description: The bus clock for either AHB and APB
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- description: The internal register configuration clock
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additionalItems: true
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clock-names:
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minItems: 2
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maxItems: 5
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items:
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- const: iahb
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- const: isfr
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additionalItems: true
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interrupts:
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maxItems: 1
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additionalProperties: true
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...
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