108 lines
3.6 KiB
YAML
108 lines
3.6 KiB
YAML
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# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
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# Copyright 2019 NXP
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%YAML 1.2
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---
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$id: "http://devicetree.org/schemas/display/imx/nxp,imx8mq-dcss.yaml#"
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$schema: "http://devicetree.org/meta-schemas/core.yaml#"
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title: iMX8MQ Display Controller Subsystem (DCSS)
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maintainers:
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- Laurentiu Palcu <laurentiu.palcu@nxp.com>
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description:
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The DCSS (display controller sub system) is used to source up to three
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display buffers, compose them, and drive a display using HDMI 2.0a(with HDCP
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2.2) or MIPI-DSI. The DCSS is intended to support up to 4kp60 displays. HDR10
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image processing capabilities are included to provide a solution capable of
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driving next generation high dynamic range displays.
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properties:
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compatible:
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const: nxp,imx8mq-dcss
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reg:
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items:
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- description: DCSS base address and size, up to IRQ steer start
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- description: DCSS BLKCTL base address and size
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interrupts:
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items:
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- description: Context loader completion and error interrupt
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- description: DTG interrupt used to signal context loader trigger time
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- description: DTG interrupt for Vblank
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interrupt-names:
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items:
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- const: ctxld
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- const: ctxld_kick
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- const: vblank
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clocks:
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items:
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- description: Display APB clock for all peripheral PIO access interfaces
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- description: Display AXI clock needed by DPR, Scaler, RTRAM_CTRL
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- description: RTRAM clock
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- description: Pixel clock, can be driven either by HDMI phy clock or MIPI
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- description: DTRC clock, needed by video decompressor
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clock-names:
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items:
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- const: apb
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- const: axi
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- const: rtrm
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- const: pix
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- const: dtrc
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assigned-clocks:
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items:
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- description: Phandle and clock specifier of IMX8MQ_CLK_DISP_AXI_ROOT
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- description: Phandle and clock specifier of IMX8MQ_CLK_DISP_RTRM
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- description: Phandle and clock specifier of either IMX8MQ_VIDEO2_PLL1_REF_SEL or
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IMX8MQ_VIDEO_PLL1_REF_SEL
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assigned-clock-parents:
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items:
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- description: Phandle and clock specifier of IMX8MQ_SYS1_PLL_800M
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- description: Phandle and clock specifier of IMX8MQ_SYS1_PLL_800M
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- description: Phandle and clock specifier of IMX8MQ_CLK_27M
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assigned-clock-rates:
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items:
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- description: Must be 800 MHz
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- description: Must be 400 MHz
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port:
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$ref: /schemas/graph.yaml#/properties/port
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description:
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A port node pointing to the input port of a HDMI/DP or MIPI display bridge.
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additionalProperties: false
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examples:
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- |
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#include <dt-bindings/clock/imx8mq-clock.h>
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dcss: display-controller@32e00000 {
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compatible = "nxp,imx8mq-dcss";
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reg = <0x32e00000 0x2d000>, <0x32e2f000 0x1000>;
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interrupts = <6>, <8>, <9>;
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interrupt-names = "ctxld", "ctxld_kick", "vblank";
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interrupt-parent = <&irqsteer>;
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clocks = <&clk IMX8MQ_CLK_DISP_APB_ROOT>, <&clk IMX8MQ_CLK_DISP_AXI_ROOT>,
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<&clk IMX8MQ_CLK_DISP_RTRM_ROOT>, <&clk IMX8MQ_VIDEO2_PLL_OUT>,
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<&clk IMX8MQ_CLK_DISP_DTRC>;
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clock-names = "apb", "axi", "rtrm", "pix", "dtrc";
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assigned-clocks = <&clk IMX8MQ_CLK_DISP_AXI>, <&clk IMX8MQ_CLK_DISP_RTRM>,
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<&clk IMX8MQ_VIDEO2_PLL1_REF_SEL>;
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assigned-clock-parents = <&clk IMX8MQ_SYS1_PLL_800M>, <&clk IMX8MQ_SYS1_PLL_800M>,
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<&clk IMX8MQ_CLK_27M>;
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assigned-clock-rates = <800000000>,
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<400000000>;
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port {
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dcss_out: endpoint {
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remote-endpoint = <&hdmi_in>;
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};
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};
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};
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