102 lines
2.7 KiB
YAML
102 lines
2.7 KiB
YAML
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# SPDX-License-Identifier: GPL-2.0-only or BSD-2-Clause
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/display/msm/dsi-phy-10nm.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: Qualcomm Display DSI 10nm PHY
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maintainers:
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- Krishna Manikandan <quic_mkrishn@quicinc.com>
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allOf:
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- $ref: dsi-phy-common.yaml#
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properties:
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compatible:
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enum:
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- qcom,dsi-phy-10nm
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- qcom,dsi-phy-10nm-8998
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reg:
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items:
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- description: dsi phy register set
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- description: dsi phy lane register set
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- description: dsi pll register set
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reg-names:
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items:
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- const: dsi_phy
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- const: dsi_phy_lane
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- const: dsi_pll
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vdds-supply:
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description: |
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Connected to DSI0_MIPI_DSI_PLL_VDDA0P9 pin for sc7180 target and
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connected to VDDA_MIPI_DSI_0_PLL_0P9 pin for sdm845 target
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qcom,phy-rescode-offset-top:
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$ref: /schemas/types.yaml#/definitions/int8-array
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maxItems: 5
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description:
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Integer array of offset for pull-up legs rescode for all five lanes.
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To offset the drive strength from the calibrated value in an increasing
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manner, -32 is the weakest and +31 is the strongest.
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items:
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minimum: -32
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maximum: 31
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qcom,phy-rescode-offset-bot:
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$ref: /schemas/types.yaml#/definitions/int8-array
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maxItems: 5
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description:
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Integer array of offset for pull-down legs rescode for all five lanes.
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To offset the drive strength from the calibrated value in a decreasing
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manner, -32 is the weakest and +31 is the strongest.
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items:
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minimum: -32
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maximum: 31
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qcom,phy-drive-ldo-level:
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$ref: "/schemas/types.yaml#/definitions/uint32"
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description:
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The PHY LDO has an amplitude tuning feature to adjust the LDO output
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for the HSTX drive. Use supported levels (mV) to offset the drive level
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from the default value.
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enum: [ 375, 400, 425, 450, 475, 500 ]
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required:
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- compatible
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- reg
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- reg-names
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unevaluatedProperties: false
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examples:
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- |
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#include <dt-bindings/clock/qcom,dispcc-sdm845.h>
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#include <dt-bindings/clock/qcom,rpmh.h>
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dsi-phy@ae94400 {
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compatible = "qcom,dsi-phy-10nm";
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reg = <0x0ae94400 0x200>,
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<0x0ae94600 0x280>,
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<0x0ae94a00 0x1e0>;
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reg-names = "dsi_phy",
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"dsi_phy_lane",
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"dsi_pll";
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#clock-cells = <1>;
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#phy-cells = <0>;
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vdds-supply = <&vdda_mipi_dsi0_pll>;
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clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
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<&rpmhcc RPMH_CXO_CLK>;
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clock-names = "iface", "ref";
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qcom,phy-rescode-offset-top = /bits/ 8 <0 0 0 0 0>;
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qcom,phy-rescode-offset-bot = /bits/ 8 <0 0 0 0 0>;
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qcom,phy-drive-ldo-level = <400>;
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};
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...
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