152 lines
4.2 KiB
YAML
152 lines
4.2 KiB
YAML
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# SPDX-License-Identifier: GPL-2.0-only or BSD-2-Clause
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/display/msm/qcom,sc8280xp-mdss.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: Qualcomm SC8280XP Mobile Display Subsystem
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maintainers:
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- Bjorn Andersson <andersson@kernel.org>
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description:
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Device tree bindings for MSM Mobile Display Subsystem (MDSS) that encapsulates
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sub-blocks like DPU display controller, DSI and DP interfaces etc.
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$ref: /schemas/display/msm/mdss-common.yaml#
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properties:
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compatible:
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const: qcom,sc8280xp-mdss
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clocks:
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items:
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- description: Display AHB clock from gcc
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- description: Display AHB clock from dispcc
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- description: Display core clock
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clock-names:
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items:
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- const: iface
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- const: ahb
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- const: core
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patternProperties:
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"^display-controller@[0-9a-f]+$":
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type: object
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properties:
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compatible:
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const: qcom,sc8280xp-dpu
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"^displayport-controller@[0-9a-f]+$":
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type: object
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properties:
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compatible:
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enum:
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- qcom,sc8280xp-dp
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- qcom,sc8280xp-edp
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unevaluatedProperties: false
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examples:
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- |
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#include <dt-bindings/clock/qcom,dispcc-sc8280xp.h>
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#include <dt-bindings/clock/qcom,gcc-sc8280xp.h>
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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#include <dt-bindings/interconnect/qcom,sc8280xp.h>
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#include <dt-bindings/power/qcom-rpmpd.h>
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display-subsystem@ae00000 {
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compatible = "qcom,sc8280xp-mdss";
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reg = <0x0ae00000 0x1000>;
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reg-names = "mdss";
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power-domains = <&dispcc0 MDSS_GDSC>;
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clocks = <&gcc GCC_DISP_AHB_CLK>,
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<&dispcc0 DISP_CC_MDSS_AHB_CLK>,
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<&dispcc0 DISP_CC_MDSS_MDP_CLK>;
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clock-names = "iface",
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"ahb",
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"core";
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resets = <&dispcc0 DISP_CC_MDSS_CORE_BCR>;
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interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-controller;
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#interrupt-cells = <1>;
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interconnects = <&mmss_noc MASTER_MDP0 0 &mc_virt SLAVE_EBI1 0>,
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<&mmss_noc MASTER_MDP1 0 &mc_virt SLAVE_EBI1 0>;
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interconnect-names = "mdp0-mem", "mdp1-mem";
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iommus = <&apps_smmu 0x1000 0x402>;
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#address-cells = <1>;
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#size-cells = <1>;
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ranges;
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display-controller@ae01000 {
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compatible = "qcom,sc8280xp-dpu";
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reg = <0x0ae01000 0x8f000>,
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<0x0aeb0000 0x2008>;
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reg-names = "mdp", "vbif";
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clocks = <&gcc GCC_DISP_HF_AXI_CLK>,
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<&gcc GCC_DISP_SF_AXI_CLK>,
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<&dispcc0 DISP_CC_MDSS_AHB_CLK>,
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<&dispcc0 DISP_CC_MDSS_MDP_LUT_CLK>,
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<&dispcc0 DISP_CC_MDSS_MDP_CLK>,
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<&dispcc0 DISP_CC_MDSS_VSYNC_CLK>;
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clock-names = "bus",
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"nrt_bus",
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"iface",
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"lut",
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"core",
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"vsync";
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assigned-clocks = <&dispcc0 DISP_CC_MDSS_VSYNC_CLK>;
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assigned-clock-rates = <19200000>;
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operating-points-v2 = <&mdss0_mdp_opp_table>;
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power-domains = <&rpmhpd SC8280XP_MMCX>;
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interrupt-parent = <&mdss0>;
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interrupts = <0>;
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ports {
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#address-cells = <1>;
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#size-cells = <0>;
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port@0 {
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reg = <0>;
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endpoint {
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remote-endpoint = <&mdss0_dp0_in>;
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};
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};
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port@4 {
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reg = <4>;
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endpoint {
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remote-endpoint = <&mdss0_dp1_in>;
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};
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};
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port@5 {
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reg = <5>;
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endpoint {
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remote-endpoint = <&mdss0_dp3_in>;
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};
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};
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port@6 {
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reg = <6>;
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endpoint {
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remote-endpoint = <&mdss0_dp2_in>;
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};
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};
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};
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};
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};
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...
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