132 lines
3.1 KiB
YAML
132 lines
3.1 KiB
YAML
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# SPDX-License-Identifier: GPL-2.0
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/display/rockchip/rockchip-vop.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: Rockchip SoC display controller (VOP)
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description:
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VOP (Video Output Processor) is the display controller for the Rockchip
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series of SoCs which transfers the image data from a video memory
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buffer to an external LCD interface.
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maintainers:
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- Sandy Huang <hjc@rock-chips.com>
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- Heiko Stuebner <heiko@sntech.de>
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properties:
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compatible:
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enum:
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- rockchip,px30-vop-big
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- rockchip,px30-vop-lit
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- rockchip,rk3036-vop
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- rockchip,rk3066-vop
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- rockchip,rk3126-vop
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- rockchip,rk3188-vop
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- rockchip,rk3228-vop
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- rockchip,rk3288-vop
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- rockchip,rk3328-vop
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- rockchip,rk3366-vop
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- rockchip,rk3368-vop
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- rockchip,rk3399-vop-big
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- rockchip,rk3399-vop-lit
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reg:
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minItems: 1
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items:
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- description:
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Must contain one entry corresponding to the base address and length
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of the register space.
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- description:
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Can optionally contain a second entry corresponding to
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the CRTC gamma LUT address.
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interrupts:
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maxItems: 1
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description:
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The VOP interrupt is shared by several interrupt sources, such as
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frame start (VSYNC), line flag and other status interrupts.
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clocks:
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items:
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- description: Clock for ddr buffer transfer.
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- description: Pixel clock.
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- description: Clock for the ahb bus to R/W the phy regs.
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clock-names:
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items:
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- const: aclk_vop
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- const: dclk_vop
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- const: hclk_vop
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resets:
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maxItems: 3
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reset-names:
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items:
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- const: axi
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- const: ahb
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- const: dclk
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port:
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$ref: /schemas/graph.yaml#/properties/port
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assigned-clocks:
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maxItems: 2
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assigned-clock-rates:
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maxItems: 2
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iommus:
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maxItems: 1
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power-domains:
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maxItems: 1
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required:
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- compatible
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- reg
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- interrupts
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- clocks
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- clock-names
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- resets
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- reset-names
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- port
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additionalProperties: false
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examples:
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- |
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#include <dt-bindings/clock/rk3288-cru.h>
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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#include <dt-bindings/power/rk3288-power.h>
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vopb: vopb@ff930000 {
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compatible = "rockchip,rk3288-vop";
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reg = <0xff930000 0x19c>,
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<0xff931000 0x1000>;
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interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&cru ACLK_VOP0>,
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<&cru DCLK_VOP0>,
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<&cru HCLK_VOP0>;
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clock-names = "aclk_vop", "dclk_vop", "hclk_vop";
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power-domains = <&power RK3288_PD_VIO>;
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resets = <&cru SRST_LCDC1_AXI>,
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<&cru SRST_LCDC1_AHB>,
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<&cru SRST_LCDC1_DCLK>;
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reset-names = "axi", "ahb", "dclk";
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iommus = <&vopb_mmu>;
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vopb_out: port {
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#address-cells = <1>;
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#size-cells = <0>;
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vopb_out_edp: endpoint@0 {
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reg = <0>;
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remote-endpoint=<&edp_in_vopb>;
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};
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vopb_out_hdmi: endpoint@1 {
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reg = <1>;
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remote-endpoint=<&hdmi_in_vopb>;
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};
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};
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};
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