150 lines
3.5 KiB
YAML
150 lines
3.5 KiB
YAML
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# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/dma/fsl,imx-sdma.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: Freescale Smart Direct Memory Access (SDMA) Controller for i.MX
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maintainers:
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- Joy Zou <joy.zou@nxp.com>
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allOf:
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- $ref: dma-controller.yaml#
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properties:
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compatible:
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oneOf:
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- items:
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- enum:
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- fsl,imx50-sdma
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- fsl,imx51-sdma
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- fsl,imx53-sdma
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- fsl,imx6q-sdma
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- fsl,imx7d-sdma
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- const: fsl,imx35-sdma
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- items:
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- enum:
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- fsl,imx6sx-sdma
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- fsl,imx6sl-sdma
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- const: fsl,imx6q-sdma
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- items:
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- const: fsl,imx6ul-sdma
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- const: fsl,imx6q-sdma
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- const: fsl,imx35-sdma
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- items:
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- const: fsl,imx6sll-sdma
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- const: fsl,imx6ul-sdma
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- items:
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- const: fsl,imx8mq-sdma
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- const: fsl,imx7d-sdma
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- items:
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- enum:
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- fsl,imx8mp-sdma
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- fsl,imx8mn-sdma
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- fsl,imx8mm-sdma
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- const: fsl,imx8mq-sdma
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- items:
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- enum:
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- fsl,imx25-sdma
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- fsl,imx31-sdma
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- fsl,imx35-sdma
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reg:
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maxItems: 1
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interrupts:
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maxItems: 1
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fsl,sdma-ram-script-name:
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$ref: /schemas/types.yaml#/definitions/string
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description: Should contain the full path of SDMA RAM scripts firmware.
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"#dma-cells":
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const: 3
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description: |
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The first cell: request/event ID
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The second cell: peripheral types ID
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enum:
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- MCU domain SSI: 0
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- Shared SSI: 1
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- MMC: 2
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- SDHC: 3
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- MCU domain UART: 4
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- Shared UART: 5
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- FIRI: 6
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- MCU domain CSPI: 7
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- Shared CSPI: 8
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- SIM: 9
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- ATA: 10
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- CCM: 11
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- External peripheral: 12
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- Memory Stick Host Controller: 13
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- Shared Memory Stick Host Controller: 14
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- DSP: 15
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- Memory: 16
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- FIFO type Memory: 17
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- SPDIF: 18
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- IPU Memory: 19
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- ASRC: 20
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- ESAI: 21
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- SSI Dual FIFO: 22
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description: needs firmware more than ver 2
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- Shared ASRC: 23
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- SAI: 24
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- HDMI Audio: 25
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The third cell: transfer priority ID
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enum:
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- High: 0
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- Medium: 1
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- Low: 2
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gpr:
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$ref: /schemas/types.yaml#/definitions/phandle
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description: The phandle to the General Purpose Register (GPR) node
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fsl,sdma-event-remap:
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$ref: /schemas/types.yaml#/definitions/uint32-matrix
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maxItems: 2
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items:
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items:
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- description: GPR register offset
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- description: GPR register shift
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- description: GPR register value
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description: |
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Register bits of sdma event remap, the format is <reg shift val>.
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The order is <RX>, <TX>.
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clocks:
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maxItems: 2
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clock-names:
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items:
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- const: ipg
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- const: ahb
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iram:
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$ref: /schemas/types.yaml#/definitions/phandle
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description: The phandle to the On-chip RAM (OCRAM) node.
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required:
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- compatible
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- reg
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- interrupts
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- fsl,sdma-ram-script-name
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additionalProperties: false
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examples:
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- |
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sdma: dma-controller@83fb0000 {
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compatible = "fsl,imx51-sdma", "fsl,imx35-sdma";
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reg = <0x83fb0000 0x4000>;
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interrupts = <6>;
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#dma-cells = <3>;
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fsl,sdma-ram-script-name = "sdma-imx51.bin";
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};
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...
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