118 lines
3.5 KiB
YAML
118 lines
3.5 KiB
YAML
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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/dma/nvidia,tegra186-gpc-dma.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: NVIDIA Tegra GPC DMA Controller
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description: |
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The Tegra General Purpose Central (GPC) DMA controller is used for faster
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data transfers between memory to memory, memory to device and device to
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memory.
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maintainers:
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- Jon Hunter <jonathanh@nvidia.com>
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- Rajesh Gumasta <rgumasta@nvidia.com>
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allOf:
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- $ref: dma-controller.yaml#
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properties:
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compatible:
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oneOf:
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- const: nvidia,tegra186-gpcdma
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- items:
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- enum:
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- nvidia,tegra234-gpcdma
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- nvidia,tegra194-gpcdma
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- const: nvidia,tegra186-gpcdma
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"#dma-cells":
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const: 1
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reg:
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maxItems: 1
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interrupts:
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description:
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Should contain all of the per-channel DMA interrupts in
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ascending order with respect to the DMA channel index.
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minItems: 1
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maxItems: 32
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resets:
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maxItems: 1
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reset-names:
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const: gpcdma
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iommus:
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maxItems: 1
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dma-coherent: true
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dma-channel-mask:
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maxItems: 1
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required:
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- compatible
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- reg
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- interrupts
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- resets
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- reset-names
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- "#dma-cells"
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- iommus
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- dma-channel-mask
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additionalProperties: false
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examples:
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- |
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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#include <dt-bindings/memory/tegra186-mc.h>
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#include <dt-bindings/reset/tegra186-reset.h>
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dma-controller@2600000 {
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compatible = "nvidia,tegra186-gpcdma";
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reg = <0x2600000 0x210000>;
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resets = <&bpmp TEGRA186_RESET_GPCDMA>;
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reset-names = "gpcdma";
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interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>;
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#dma-cells = <1>;
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iommus = <&smmu TEGRA186_SID_GPCDMA_0>;
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dma-coherent;
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dma-channel-mask = <0xfffffffe>;
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};
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...
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