133 lines
3.8 KiB
YAML
133 lines
3.8 KiB
YAML
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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/dma/renesas,rz-dmac.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: Renesas RZ/{G2L,G2UL,V2L} DMA Controller
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maintainers:
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- Biju Das <biju.das.jz@bp.renesas.com>
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allOf:
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- $ref: dma-controller.yaml#
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properties:
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compatible:
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items:
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- enum:
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- renesas,r9a07g043-dmac # RZ/G2UL
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- renesas,r9a07g044-dmac # RZ/G2{L,LC}
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- renesas,r9a07g054-dmac # RZ/V2L
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- const: renesas,rz-dmac
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reg:
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items:
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- description: Control and channel register block
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- description: DMA extended resource selector block
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interrupts:
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maxItems: 17
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interrupt-names:
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items:
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- const: error
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- const: ch0
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- const: ch1
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- const: ch2
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- const: ch3
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- const: ch4
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- const: ch5
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- const: ch6
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- const: ch7
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- const: ch8
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- const: ch9
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- const: ch10
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- const: ch11
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- const: ch12
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- const: ch13
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- const: ch14
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- const: ch15
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clocks:
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items:
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- description: DMA main clock
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- description: DMA register access clock
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'#dma-cells':
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const: 1
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description:
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The cell specifies the encoded MID/RID values of the DMAC port
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connected to the DMA client and the slave channel configuration
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parameters.
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bits[0:9] - Specifies MID/RID value
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bit[10] - Specifies DMA request high enable (HIEN)
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bit[11] - Specifies DMA request detection type (LVL)
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bits[12:14] - Specifies DMAACK output mode (AM)
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bit[15] - Specifies Transfer Mode (TM)
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dma-channels:
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const: 16
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power-domains:
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maxItems: 1
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resets:
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items:
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- description: Reset for DMA ARESETN reset terminal
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- description: Reset for DMA RST_ASYNC reset terminal
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required:
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- compatible
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- reg
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- interrupts
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- interrupt-names
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- clocks
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- '#dma-cells'
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- dma-channels
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- power-domains
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- resets
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additionalProperties: false
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examples:
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- |
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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#include <dt-bindings/clock/r9a07g044-cpg.h>
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dmac: dma-controller@11820000 {
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compatible = "renesas,r9a07g044-dmac",
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"renesas,rz-dmac";
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reg = <0x11820000 0x10000>,
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<0x11830000 0x10000>;
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interrupts = <GIC_SPI 141 IRQ_TYPE_EDGE_RISING>,
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<GIC_SPI 125 IRQ_TYPE_EDGE_RISING>,
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<GIC_SPI 126 IRQ_TYPE_EDGE_RISING>,
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<GIC_SPI 127 IRQ_TYPE_EDGE_RISING>,
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<GIC_SPI 128 IRQ_TYPE_EDGE_RISING>,
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<GIC_SPI 129 IRQ_TYPE_EDGE_RISING>,
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<GIC_SPI 130 IRQ_TYPE_EDGE_RISING>,
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<GIC_SPI 131 IRQ_TYPE_EDGE_RISING>,
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<GIC_SPI 132 IRQ_TYPE_EDGE_RISING>,
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<GIC_SPI 133 IRQ_TYPE_EDGE_RISING>,
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<GIC_SPI 134 IRQ_TYPE_EDGE_RISING>,
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<GIC_SPI 135 IRQ_TYPE_EDGE_RISING>,
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<GIC_SPI 136 IRQ_TYPE_EDGE_RISING>,
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<GIC_SPI 137 IRQ_TYPE_EDGE_RISING>,
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<GIC_SPI 138 IRQ_TYPE_EDGE_RISING>,
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<GIC_SPI 139 IRQ_TYPE_EDGE_RISING>,
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<GIC_SPI 140 IRQ_TYPE_EDGE_RISING>;
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interrupt-names = "error",
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"ch0", "ch1", "ch2", "ch3",
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"ch4", "ch5", "ch6", "ch7",
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"ch8", "ch9", "ch10", "ch11",
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"ch12", "ch13", "ch14", "ch15";
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clocks = <&cpg CPG_MOD R9A07G044_DMAC_ACLK>,
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<&cpg CPG_MOD R9A07G044_DMAC_PCLK>;
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power-domains = <&cpg>;
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resets = <&cpg R9A07G044_DMAC_ARESETN>,
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<&cpg R9A07G044_DMAC_RST_ASYNC>;
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#dma-cells = <1>;
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dma-channels = <16>;
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};
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