160 lines
4.9 KiB
YAML
160 lines
4.9 KiB
YAML
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# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/dma/stericsson,dma40.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: ST-Ericsson DMA40 DMA Engine
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maintainers:
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- Linus Walleij <linus.walleij@linaro.org>
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allOf:
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- $ref: dma-controller.yaml#
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properties:
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"#dma-cells":
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const: 3
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description: |
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The first cell is the unique device channel number as indicated by this
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table for DB8500 which is the only ASIC known to use DMA40:
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0: SPI controller 0
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1: SD/MMC controller 0 (unused)
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2: SD/MMC controller 1 (unused)
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3: SD/MMC controller 2 (unused)
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4: I2C port 1
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5: I2C port 3
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6: I2C port 2
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7: I2C port 4
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8: Synchronous Serial Port SSP0
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9: Synchronous Serial Port SSP1
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10: Multi-Channel Display Engine MCDE RX
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11: UART port 2
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12: UART port 1
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13: UART port 0
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14: Multirate Serial Port MSP2
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15: I2C port 0
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16: USB OTG in/out endpoints 7 & 15
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17: USB OTG in/out endpoints 6 & 14
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18: USB OTG in/out endpoints 5 & 13
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19: USB OTG in/out endpoints 4 & 12
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20: SLIMbus or HSI channel 0
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21: SLIMbus or HSI channel 1
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22: SLIMbus or HSI channel 2
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23: SLIMbus or HSI channel 3
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24: Multimedia DSP SXA0
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25: Multimedia DSP SXA1
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26: Multimedia DSP SXA2
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27: Multimedia DSP SXA3
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28: SD/MMC controller 2
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29: SD/MMC controller 0
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30: MSP port 1 on DB8500 v1, MSP port 3 on DB8500 v2
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31: MSP port 0 or SLIMbus channel 0
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32: SD/MMC controller 1
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33: SPI controller 2
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34: i2c3 RX2 TX2
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35: SPI controller 1
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36: USB OTG in/out endpoints 3 & 11
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37: USB OTG in/out endpoints 2 & 10
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38: USB OTG in/out endpoints 1 & 9
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39: USB OTG in/out endpoints 8
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40: SPI controller 3
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41: SD/MMC controller 3
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42: SD/MMC controller 4
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43: SD/MMC controller 5
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44: Multimedia DSP SXA4
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45: Multimedia DSP SXA5
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46: SLIMbus channel 8 or Multimedia DSP SXA6
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47: SLIMbus channel 9 or Multimedia DSP SXA7
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48: Crypto Accelerator 1
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49: Crypto Accelerator 1 TX or Hash Accelerator 1 TX
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50: Hash Accelerator 1 TX
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51: memcpy TX (to be used by the DMA driver for memcpy operations)
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52: SLIMbus or HSI channel 4
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53: SLIMbus or HSI channel 5
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54: SLIMbus or HSI channel 6
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55: SLIMbus or HSI channel 7
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56: memcpy (to be used by the DMA driver for memcpy operations)
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57: memcpy (to be used by the DMA driver for memcpy operations)
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58: memcpy (to be used by the DMA driver for memcpy operations)
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59: memcpy (to be used by the DMA driver for memcpy operations)
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60: memcpy (to be used by the DMA driver for memcpy operations)
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61: Crypto Accelerator 0
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62: Crypto Accelerator 0 TX or Hash Accelerator 0 TX
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63: Hash Accelerator 0 TX
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The second cell is the DMA request line number. This is only used when
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a fixed channel is allocated, and indicated by setting bit 3 in the
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flags field (see below).
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The third cell is a 32bit flags bitfield with the following possible
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bits set:
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0x00000001 (bit 0) - mode:
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Logical channel when unset
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Physical channel when set
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0x00000002 (bit 1) - direction:
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Memory to Device when unset
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Device to Memory when set
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0x00000004 (bit 2) - endianness:
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Little endian when unset
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Big endian when set
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0x00000008 (bit 3) - use fixed channel:
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Use automatic channel selection when unset
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Use DMA request line number when set
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0x00000010 (bit 4) - set channel as high priority:
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Normal priority when unset
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High priority when set
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compatible:
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items:
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- const: stericsson,db8500-dma40
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- const: stericsson,dma40
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reg:
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items:
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- description: DMA40 memory base
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- description: LCPA memory base
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reg-names:
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items:
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- const: base
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- const: lcpa
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interrupts:
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maxItems: 1
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clocks:
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maxItems: 1
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memcpy-channels:
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$ref: /schemas/types.yaml#/definitions/uint32-array
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description: Array of u32 elements indicating which channels on the DMA
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engine are elegible for memcpy transfers
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required:
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- "#dma-cells"
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- compatible
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- reg
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- interrupts
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- clocks
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- memcpy-channels
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additionalProperties: false
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examples:
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- |
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#include <dt-bindings/interrupt-controller/irq.h>
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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#include <dt-bindings/mfd/dbx500-prcmu.h>
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dma-controller@801c0000 {
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compatible = "stericsson,db8500-dma40", "stericsson,dma40";
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reg = <0x801c0000 0x1000>, <0x40010000 0x800>;
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reg-names = "base", "lcpa";
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interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
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#dma-cells = <3>;
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memcpy-channels = <56 57 58 59 60>;
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clocks = <&prcmu_clk PRCMU_DMACLK>;
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};
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...
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