69 lines
1.4 KiB
YAML
69 lines
1.4 KiB
YAML
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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/dma/xilinx/xlnx,zynqmp-dpdma.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: Xilinx ZynqMP DisplayPort DMA Controller
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description: |
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These bindings describe the DMA engine included in the Xilinx ZynqMP
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DisplayPort Subsystem. The DMA engine supports up to 6 DMA channels (3
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channels for a video stream, 1 channel for a graphics stream, and 2 channels
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for an audio stream).
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maintainers:
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- Laurent Pinchart <laurent.pinchart@ideasonboard.com>
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allOf:
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- $ref: "../dma-controller.yaml#"
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properties:
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"#dma-cells":
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const: 1
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description: |
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The cell is the DMA channel ID (see dt-bindings/dma/xlnx-zynqmp-dpdma.h
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for a list of channel IDs).
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compatible:
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const: xlnx,zynqmp-dpdma
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reg:
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maxItems: 1
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interrupts:
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maxItems: 1
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clocks:
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description: The AXI clock
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maxItems: 1
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clock-names:
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const: axi_clk
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required:
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- "#dma-cells"
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- compatible
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- reg
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- interrupts
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- clocks
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- clock-names
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additionalProperties: false
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examples:
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- |
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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dma: dma-controller@fd4c0000 {
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compatible = "xlnx,zynqmp-dpdma";
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reg = <0xfd4c0000 0x1000>;
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interrupts = <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-parent = <&gic>;
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clocks = <&dpdma_clk>;
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clock-names = "axi_clk";
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#dma-cells = <1>;
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};
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...
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