40 lines
980 B
Plaintext
40 lines
980 B
Plaintext
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* Altera I2C Controller
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* This is Altera's synthesizable logic block I2C Controller for use
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* in Altera's FPGAs.
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Required properties :
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- compatible : should be "altr,softip-i2c-v1.0"
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- reg : Offset and length of the register set for the device
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- interrupts : <IRQ> where IRQ is the interrupt number.
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- clocks : phandle to input clock.
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- #address-cells = <1>;
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- #size-cells = <0>;
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Recommended properties :
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- clock-frequency : desired I2C bus clock frequency in Hz.
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Optional properties :
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- fifo-size : Size of the RX and TX FIFOs in bytes.
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- Child nodes conforming to i2c bus binding
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Example :
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i2c@100080000 {
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compatible = "altr,softip-i2c-v1.0";
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reg = <0x00000001 0x00080000 0x00000040>;
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interrupt-parent = <&intc>;
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interrupts = <0 43 4>;
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clocks = <&clk_0>;
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clock-frequency = <100000>;
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#address-cells = <1>;
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#size-cells = <0>;
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fifo-size = <4>;
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eeprom@51 {
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compatible = "atmel,24c32";
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reg = <0x51>;
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pagesize = <32>;
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};
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};
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