89 lines
2.2 KiB
YAML
89 lines
2.2 KiB
YAML
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# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/iio/adc/fsl,vf610-adc.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: ADC found on Freescale vf610 and similar SoCs
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maintainers:
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- Haibo Chen <haibo.chen@nxp.com>
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description:
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ADCs found on vf610/i.MX6slx and upward SoCs from Freescale.
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properties:
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compatible:
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oneOf:
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- items:
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- enum:
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- fsl,imx6sx-adc
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- fsl,imx6ul-adc
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- const: fsl,vf610-adc
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- items:
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- const: fsl,vf610-adc
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reg:
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maxItems: 1
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interrupts:
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maxItems: 1
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clocks:
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description: ADC source clock (ipg clock)
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maxItems: 1
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clock-names:
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const: adc
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vref-supply:
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description: ADC reference voltage supply.
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fsl,adck-max-frequency:
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$ref: /schemas/types.yaml#/definitions/uint32-array
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minItems: 3
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maxItems: 3
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description: |
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Maximum frequencies from datasheet operating requirements.
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Three values necessary to cover the 3 conversion modes.
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* Frequency in normal mode (ADLPC=0, ADHSC=0)
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* Frequency in high-speed mode (ADLPC=0, ADHSC=1)
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* Frequency in low-power mode (ADLPC=1, ADHSC=0)
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min-sample-time:
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$ref: /schemas/types.yaml#/definitions/uint32
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description:
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Minimum sampling time in nanoseconds. This value has
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to be chosen according to the conversion mode and the connected analog
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source resistance (R_as) and capacitance (C_as). Refer the datasheet's
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operating requirements. A safe default across a wide range of R_as and
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C_as as well as conversion modes is 1000ns.
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"#io-channel-cells":
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const: 1
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required:
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- compatible
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- reg
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- interrupts
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- clocks
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- clock-names
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- vref-supply
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additionalProperties: false
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examples:
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- |
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#include <dt-bindings/clock/vf610-clock.h>
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adc@4003b000 {
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compatible = "fsl,vf610-adc";
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reg = <0x4003b000 0x1000>;
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interrupts = <0 53 0x04>;
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clocks = <&clks VF610_CLK_ADC0>;
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clock-names = "adc";
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fsl,adck-max-frequency = <30000000>, <40000000>, <20000000>;
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vref-supply = <®_vcc_3v3_mcu>;
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min-sample-time = <10000>;
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};
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...
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