609 lines
16 KiB
YAML
609 lines
16 KiB
YAML
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# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/iio/adc/st,stm32-adc.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: STMicroelectronics STM32 ADC
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description: |
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STM32 ADC is a successive approximation analog-to-digital converter.
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It has several multiplexed input channels. Conversions can be performed
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in single, continuous, scan or discontinuous mode. Result of the ADC is
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stored in a left-aligned or right-aligned 32-bit data register.
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Conversions can be launched in software or using hardware triggers.
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The analog watchdog feature allows the application to detect if the input
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voltage goes beyond the user-defined, higher or lower thresholds.
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Each STM32 ADC block can have up to 3 ADC instances.
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maintainers:
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- Fabrice Gasnier <fabrice.gasnier@foss.st.com>
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properties:
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compatible:
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enum:
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- st,stm32f4-adc-core
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- st,stm32h7-adc-core
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- st,stm32mp1-adc-core
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- st,stm32mp13-adc-core
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reg:
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maxItems: 1
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interrupts:
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description: |
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One or more interrupts for ADC block, depending on part used:
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- stm32f4 and stm32h7 share a common ADC interrupt line.
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- stm32mp1 has two separate interrupt lines, one for each ADC within
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ADC block.
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- stm32mp13 has an interrupt line per ADC block.
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minItems: 1
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maxItems: 2
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clocks:
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minItems: 1
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maxItems: 2
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description: |
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Core can use up to two clocks, depending on part used:
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- "adc" clock: for the analog circuitry, common to all ADCs.
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It's required on stm32f4.
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It's optional on stm32h7 and stm32mp1.
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- "bus" clock: for registers access, common to all ADCs.
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It's not present on stm32f4.
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It's required on stm32h7 and stm32mp1.
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clock-names: true
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st,max-clk-rate-hz:
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description:
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Allow to specify desired max clock rate used by analog circuitry.
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vdda-supply:
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description: Phandle to the vdda input analog voltage.
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vref-supply:
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description: Phandle to the vref input analog reference voltage.
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booster-supply:
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description:
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Phandle to the embedded booster regulator that can be used to supply ADC
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analog input switches on stm32h7 and stm32mp1.
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vdd-supply:
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description:
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Phandle to the vdd input voltage. It can be used to supply ADC analog
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input switches on stm32mp1.
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st,syscfg:
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description:
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Phandle to system configuration controller. It can be used to control the
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analog circuitry on stm32mp1.
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$ref: /schemas/types.yaml#/definitions/phandle-array
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interrupt-controller: true
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'#interrupt-cells':
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const: 1
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'#address-cells':
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const: 1
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'#size-cells':
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const: 0
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allOf:
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- if:
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properties:
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compatible:
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contains:
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const: st,stm32f4-adc-core
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then:
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properties:
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clocks:
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maxItems: 1
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clock-names:
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const: adc
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interrupts:
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items:
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- description: interrupt line common for all ADCs
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st,max-clk-rate-hz:
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minimum: 600000
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maximum: 36000000
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default: 36000000
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booster-supply: false
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vdd-supply: false
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st,syscfg: false
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- if:
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properties:
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compatible:
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contains:
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const: st,stm32h7-adc-core
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then:
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properties:
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clocks:
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minItems: 1
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maxItems: 2
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clock-names:
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items:
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- const: bus
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- const: adc
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minItems: 1
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interrupts:
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items:
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- description: interrupt line common for all ADCs
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st,max-clk-rate-hz:
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minimum: 120000
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maximum: 36000000
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default: 36000000
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vdd-supply: false
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st,syscfg: false
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- if:
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properties:
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compatible:
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contains:
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const: st,stm32mp1-adc-core
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then:
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properties:
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clocks:
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minItems: 1
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maxItems: 2
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clock-names:
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items:
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- const: bus
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- const: adc
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minItems: 1
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interrupts:
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items:
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- description: interrupt line for ADC1
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- description: interrupt line for ADC2
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st,max-clk-rate-hz:
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minimum: 120000
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maximum: 36000000
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default: 36000000
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- if:
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properties:
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compatible:
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contains:
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const: st,stm32mp13-adc-core
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then:
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properties:
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clocks:
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minItems: 1
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maxItems: 2
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clock-names:
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items:
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- const: bus
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- const: adc
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minItems: 1
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interrupts:
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items:
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- description: ADC interrupt line
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st,max-clk-rate-hz:
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minimum: 150000
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maximum: 75000000
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default: 75000000
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additionalProperties: false
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required:
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- compatible
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- reg
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- interrupts
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- clocks
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- clock-names
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- vdda-supply
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- vref-supply
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- interrupt-controller
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- '#interrupt-cells'
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- '#address-cells'
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- '#size-cells'
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patternProperties:
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"^adc@[0-9]+$":
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type: object
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description:
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An ADC block node should contain at least one subnode, representing an
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ADC instance available on the machine.
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properties:
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compatible:
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enum:
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- st,stm32f4-adc
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- st,stm32h7-adc
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- st,stm32mp1-adc
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- st,stm32mp13-adc
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reg:
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description: |
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Offset of ADC instance in ADC block. Valid values are:
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- 0x0: ADC1
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- 0x100: ADC2
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- 0x200: ADC3 (stm32f4 only)
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maxItems: 1
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'#io-channel-cells':
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const: 1
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'#address-cells':
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const: 1
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'#size-cells':
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const: 0
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interrupts:
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description: |
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IRQ Line for the ADC instance. Valid values are:
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- 0 for adc@0 (single adc for stm32mp13)
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- 1 for adc@100
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- 2 for adc@200 (stm32f4 only)
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maxItems: 1
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clocks:
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description:
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Input clock private to this ADC instance. It's required only on
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stm32f4, that has per instance clock input for registers access.
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maxItems: 1
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dmas:
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description: RX DMA Channel
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maxItems: 1
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dma-names:
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const: rx
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assigned-resolution-bits:
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description: |
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Resolution (bits) to use for conversions:
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- can be 6, 8, 10 or 12 on stm32f4 and stm32mp13
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- can be 8, 10, 12, 14 or 16 on stm32h7 and stm32mp1
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st,adc-channels:
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description: |
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List of single-ended channels muxed for this ADC. It can have up to:
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- 16 channels, numbered from 0 to 15 (for in0..in15) on stm32f4
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- 19 channels, numbered from 0 to 18 (for in0..in18) on stm32mp13.
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- 20 channels, numbered from 0 to 19 (for in0..in19) on stm32h7 and
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stm32mp1.
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$ref: /schemas/types.yaml#/definitions/uint32-array
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deprecated: true
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st,adc-diff-channels:
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description: |
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List of differential channels muxed for this ADC. Some channels can
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be configured as differential instead of single-ended on stm32h7 and
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on stm32mp1. Positive and negative inputs pairs are listed:
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<vinp vinn>, <vinp vinn>,... vinp and vinn are numbered from 0 to 19.
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Note: At least one of "st,adc-channels" or "st,adc-diff-channels" is
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required if no adc generic channel is defined. These legacy channel
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properties are exclusive with adc generic channel bindings.
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Both properties can be used together. Some channels can be
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used as single-ended and some other ones as differential (mixed). But
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channels can't be configured both as single-ended and differential.
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$ref: /schemas/types.yaml#/definitions/uint32-matrix
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items:
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items:
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- description: |
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"vinp" indicates positive input number
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minimum: 0
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maximum: 19
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- description: |
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"vinn" indicates negative input number
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minimum: 0
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maximum: 19
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deprecated: true
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st,min-sample-time-nsecs:
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description:
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Minimum sampling time in nanoseconds. Depending on hardware (board)
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e.g. high/low analog input source impedance, fine tune of ADC
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sampling time may be recommended. This can be either one value or an
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array that matches "st,adc-channels" and/or "st,adc-diff-channels"
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list, to set sample time resp. for all channels, or independently for
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each channel.
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$ref: /schemas/types.yaml#/definitions/uint32-array
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deprecated: true
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nvmem-cells:
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items:
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- description: Phandle to the calibration vrefint data provided by otp
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nvmem-cell-names:
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items:
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- const: vrefint
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patternProperties:
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"^channel@([0-9]|1[0-9])$":
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type: object
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$ref: adc.yaml
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description: Represents the external channels which are connected to the ADC.
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properties:
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reg:
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items:
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minimum: 0
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maximum: 19
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label:
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description: |
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Unique name to identify which channel this is.
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Reserved label names "vddcore", "vddcpu", "vddq_ddr", "vrefint" and "vbat"
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are used to identify internal channels with matching names.
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diff-channels:
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$ref: /schemas/types.yaml#/definitions/uint32-array
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items:
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minimum: 0
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maximum: 19
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st,min-sample-time-ns:
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description: |
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Minimum sampling time in nanoseconds. Depending on hardware (board)
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e.g. high/low analog input source impedance, fine tune of ADC
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sampling time may be recommended.
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required:
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- reg
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additionalProperties: false
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allOf:
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- if:
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properties:
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compatible:
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contains:
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const: st,stm32f4-adc
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then:
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properties:
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reg:
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enum:
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- 0x0
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- 0x100
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- 0x200
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interrupts:
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minimum: 0
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maximum: 2
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assigned-resolution-bits:
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enum: [6, 8, 10, 12]
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default: 12
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st,adc-channels:
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minItems: 1
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maxItems: 16
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items:
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minimum: 0
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maximum: 15
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st,adc-diff-channels: false
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st,min-sample-time-nsecs:
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minItems: 1
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maxItems: 16
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items:
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minimum: 80
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required:
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- clocks
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- if:
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properties:
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compatible:
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contains:
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enum:
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- st,stm32h7-adc
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- st,stm32mp1-adc
|
||
|
|
|
||
|
|
then:
|
||
|
|
properties:
|
||
|
|
reg:
|
||
|
|
enum:
|
||
|
|
- 0x0
|
||
|
|
- 0x100
|
||
|
|
|
||
|
|
interrupts:
|
||
|
|
minimum: 0
|
||
|
|
maximum: 1
|
||
|
|
|
||
|
|
assigned-resolution-bits:
|
||
|
|
enum: [8, 10, 12, 14, 16]
|
||
|
|
default: 16
|
||
|
|
|
||
|
|
st,adc-channels:
|
||
|
|
minItems: 1
|
||
|
|
maxItems: 20
|
||
|
|
items:
|
||
|
|
minimum: 0
|
||
|
|
maximum: 19
|
||
|
|
|
||
|
|
st,min-sample-time-nsecs:
|
||
|
|
minItems: 1
|
||
|
|
maxItems: 20
|
||
|
|
items:
|
||
|
|
minimum: 40
|
||
|
|
|
||
|
|
|
||
|
|
- if:
|
||
|
|
properties:
|
||
|
|
compatible:
|
||
|
|
contains:
|
||
|
|
const: st,stm32mp13-adc
|
||
|
|
|
||
|
|
then:
|
||
|
|
properties:
|
||
|
|
reg:
|
||
|
|
const: 0x0
|
||
|
|
|
||
|
|
interrupts:
|
||
|
|
const: 0
|
||
|
|
|
||
|
|
assigned-resolution-bits:
|
||
|
|
enum: [6, 8, 10, 12]
|
||
|
|
default: 12
|
||
|
|
|
||
|
|
st,adc-channels:
|
||
|
|
minItems: 1
|
||
|
|
maxItems: 19
|
||
|
|
items:
|
||
|
|
minimum: 0
|
||
|
|
maximum: 18
|
||
|
|
|
||
|
|
st,min-sample-time-nsecs:
|
||
|
|
minItems: 1
|
||
|
|
maxItems: 19
|
||
|
|
items:
|
||
|
|
minimum: 40
|
||
|
|
additionalProperties: false
|
||
|
|
|
||
|
|
required:
|
||
|
|
- compatible
|
||
|
|
- reg
|
||
|
|
- interrupts
|
||
|
|
- '#io-channel-cells'
|
||
|
|
|
||
|
|
examples:
|
||
|
|
- |
|
||
|
|
// Example 1: with stm32f429, ADC1, single-ended channel 8
|
||
|
|
adc123: adc@40012000 {
|
||
|
|
compatible = "st,stm32f4-adc-core";
|
||
|
|
reg = <0x40012000 0x400>;
|
||
|
|
interrupts = <18>;
|
||
|
|
clocks = <&rcc 0 168>;
|
||
|
|
clock-names = "adc";
|
||
|
|
st,max-clk-rate-hz = <36000000>;
|
||
|
|
vdda-supply = <&vdda>;
|
||
|
|
vref-supply = <&vref>;
|
||
|
|
interrupt-controller;
|
||
|
|
#interrupt-cells = <1>;
|
||
|
|
#address-cells = <1>;
|
||
|
|
#size-cells = <0>;
|
||
|
|
adc@0 {
|
||
|
|
compatible = "st,stm32f4-adc";
|
||
|
|
#io-channel-cells = <1>;
|
||
|
|
reg = <0x0>;
|
||
|
|
clocks = <&rcc 0 168>;
|
||
|
|
interrupt-parent = <&adc123>;
|
||
|
|
interrupts = <0>;
|
||
|
|
st,adc-channels = <8>;
|
||
|
|
dmas = <&dma2 0 0 0x400 0x0>;
|
||
|
|
dma-names = "rx";
|
||
|
|
assigned-resolution-bits = <8>;
|
||
|
|
};
|
||
|
|
// ...
|
||
|
|
// other adc child nodes follow...
|
||
|
|
};
|
||
|
|
|
||
|
|
- |
|
||
|
|
// Example 2: with stm32mp157c to setup ADC1 with:
|
||
|
|
// - channels 0 & 1 as single-ended
|
||
|
|
// - channels 2 & 3 as differential (with resp. 6 & 7 negative inputs)
|
||
|
|
#include <dt-bindings/interrupt-controller/arm-gic.h>
|
||
|
|
#include <dt-bindings/clock/stm32mp1-clks.h>
|
||
|
|
adc12: adc@48003000 {
|
||
|
|
compatible = "st,stm32mp1-adc-core";
|
||
|
|
reg = <0x48003000 0x400>;
|
||
|
|
interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>,
|
||
|
|
<GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>;
|
||
|
|
clocks = <&rcc ADC12>, <&rcc ADC12_K>;
|
||
|
|
clock-names = "bus", "adc";
|
||
|
|
booster-supply = <&booster>;
|
||
|
|
vdd-supply = <&vdd>;
|
||
|
|
vdda-supply = <&vdda>;
|
||
|
|
vref-supply = <&vref>;
|
||
|
|
st,syscfg = <&syscfg>;
|
||
|
|
interrupt-controller;
|
||
|
|
#interrupt-cells = <1>;
|
||
|
|
#address-cells = <1>;
|
||
|
|
#size-cells = <0>;
|
||
|
|
adc@0 {
|
||
|
|
compatible = "st,stm32mp1-adc";
|
||
|
|
#io-channel-cells = <1>;
|
||
|
|
reg = <0x0>;
|
||
|
|
interrupt-parent = <&adc12>;
|
||
|
|
interrupts = <0>;
|
||
|
|
st,adc-channels = <0 1>;
|
||
|
|
st,adc-diff-channels = <2 6>, <3 7>;
|
||
|
|
st,min-sample-time-nsecs = <5000>;
|
||
|
|
dmas = <&dmamux1 9 0x400 0x05>;
|
||
|
|
dma-names = "rx";
|
||
|
|
};
|
||
|
|
// ...
|
||
|
|
// other adc child node follow...
|
||
|
|
};
|
||
|
|
|
||
|
|
- |
|
||
|
|
// Example 3: with stm32mp157c to setup ADC2 with:
|
||
|
|
// - internal channels 13, 14, 15.
|
||
|
|
#include <dt-bindings/interrupt-controller/arm-gic.h>
|
||
|
|
#include <dt-bindings/clock/stm32mp1-clks.h>
|
||
|
|
adc122: adc@48003000 {
|
||
|
|
compatible = "st,stm32mp1-adc-core";
|
||
|
|
reg = <0x48003000 0x400>;
|
||
|
|
interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>,
|
||
|
|
<GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>;
|
||
|
|
clocks = <&rcc ADC12>, <&rcc ADC12_K>;
|
||
|
|
clock-names = "bus", "adc";
|
||
|
|
booster-supply = <&booster>;
|
||
|
|
vdd-supply = <&vdd>;
|
||
|
|
vdda-supply = <&vdda>;
|
||
|
|
vref-supply = <&vref>;
|
||
|
|
st,syscfg = <&syscfg>;
|
||
|
|
interrupt-controller;
|
||
|
|
#interrupt-cells = <1>;
|
||
|
|
#address-cells = <1>;
|
||
|
|
#size-cells = <0>;
|
||
|
|
adc@100 {
|
||
|
|
compatible = "st,stm32mp1-adc";
|
||
|
|
#io-channel-cells = <1>;
|
||
|
|
reg = <0x100>;
|
||
|
|
interrupts = <1>;
|
||
|
|
#address-cells = <1>;
|
||
|
|
#size-cells = <0>;
|
||
|
|
channel@13 {
|
||
|
|
reg = <13>;
|
||
|
|
label = "vrefint";
|
||
|
|
st,min-sample-time-ns = <9000>;
|
||
|
|
};
|
||
|
|
channel@14 {
|
||
|
|
reg = <14>;
|
||
|
|
label = "vddcore";
|
||
|
|
st,min-sample-time-ns = <9000>;
|
||
|
|
};
|
||
|
|
channel@15 {
|
||
|
|
reg = <15>;
|
||
|
|
label = "vbat";
|
||
|
|
st,min-sample-time-ns = <9000>;
|
||
|
|
};
|
||
|
|
};
|
||
|
|
};
|
||
|
|
|
||
|
|
...
|