92 lines
2.6 KiB
YAML
92 lines
2.6 KiB
YAML
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# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/interrupt-controller/qcom,pdc.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: PDC interrupt controller
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maintainers:
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- Bjorn Andersson <bjorn.andersson@linaro.org>
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description: |
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Qualcomm Technologies Inc. SoCs based on the RPM Hardened architecture have a
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Power Domain Controller (PDC) that is on always-on domain. In addition to
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providing power control for the power domains, the hardware also has an
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interrupt controller that can be used to help detect edge low interrupts as
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well detect interrupts when the GIC is non-operational.
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GIC is parent interrupt controller at the highest level. Platform interrupt
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controller PDC is next in hierarchy, followed by others. Drivers requiring
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wakeup capabilities of their device interrupts routed through the PDC, must
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specify PDC as their interrupt controller and request the PDC port associated
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with the GIC interrupt. See example below.
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properties:
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compatible:
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items:
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- enum:
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- qcom,sc7180-pdc
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- qcom,sc7280-pdc
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- qcom,sc8280xp-pdc
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- qcom,sdm845-pdc
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- qcom,sdx55-pdc
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- qcom,sdx65-pdc
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- qcom,sm6350-pdc
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- qcom,sm8150-pdc
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- qcom,sm8250-pdc
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- qcom,sm8350-pdc
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- qcom,sm8450-pdc
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- const: qcom,pdc
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reg:
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minItems: 1
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items:
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- description: PDC base register region
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- description: Edge or Level config register for SPI interrupts
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'#interrupt-cells':
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const: 2
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interrupt-controller: true
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qcom,pdc-ranges:
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$ref: /schemas/types.yaml#/definitions/uint32-matrix
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minItems: 1
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maxItems: 32 # no hard limit
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items:
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items:
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- description: starting PDC port
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- description: GIC hwirq number for the PDC port
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- description: number of interrupts in sequence
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description: |
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Specifies the PDC pin offset and the number of PDC ports.
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The tuples indicates the valid mapping of valid PDC ports
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and their hwirq mapping.
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required:
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- compatible
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- reg
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- '#interrupt-cells'
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- interrupt-controller
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- qcom,pdc-ranges
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additionalProperties: false
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examples:
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- |
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#include <dt-bindings/interrupt-controller/irq.h>
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pdc: interrupt-controller@b220000 {
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compatible = "qcom,sdm845-pdc", "qcom,pdc";
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reg = <0xb220000 0x30000>;
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qcom,pdc-ranges = <0 512 94>, <94 641 15>, <115 662 7>;
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#interrupt-cells = <2>;
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interrupt-parent = <&intc>;
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interrupt-controller;
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};
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wake-device {
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interrupts-extended = <&pdc 2 IRQ_TYPE_LEVEL_HIGH>;
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};
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