81 lines
2.1 KiB
YAML
81 lines
2.1 KiB
YAML
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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/interrupt-controller/renesas,rza1-irqc.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: Renesas RZ/A1 Interrupt Controller
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maintainers:
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- Chris Brandt <chris.brandt@renesas.com>
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- Geert Uytterhoeven <geert+renesas@glider.be>
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description: |
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The RZ/A1 Interrupt Controller is a front-end for the GIC found on Renesas RZ/A1 and
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RZ/A2 SoCs:
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- IRQ sense select for 8 external interrupts, 1:1-mapped to 8 GIC SPI interrupts,
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- NMI edge select.
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allOf:
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- $ref: /schemas/interrupt-controller.yaml#
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properties:
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compatible:
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items:
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- enum:
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- renesas,r7s72100-irqc # RZ/A1H
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- renesas,r7s9210-irqc # RZ/A2M
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- const: renesas,rza1-irqc
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'#interrupt-cells':
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const: 2
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'#address-cells':
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const: 0
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interrupt-controller: true
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reg:
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maxItems: 1
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interrupt-map:
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maxItems: 8
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description: Specifies the mapping from external interrupts to GIC interrupts.
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interrupt-map-mask:
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items:
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- const: 7
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- const: 0
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required:
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- compatible
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- '#interrupt-cells'
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- '#address-cells'
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- interrupt-controller
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- reg
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- interrupt-map
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- interrupt-map-mask
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additionalProperties: false
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examples:
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- |
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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irqc: interrupt-controller@fcfef800 {
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compatible = "renesas,r7s72100-irqc", "renesas,rza1-irqc";
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#interrupt-cells = <2>;
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#address-cells = <0>;
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interrupt-controller;
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reg = <0xfcfef800 0x6>;
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interrupt-map =
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<0 0 &gic GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
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<1 0 &gic GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
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<2 0 &gic GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
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<3 0 &gic GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
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<4 0 &gic GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
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<5 0 &gic GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>,
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<6 0 &gic GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>,
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<7 0 &gic GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-map-mask = <7 0>;
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};
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