191 lines
4.5 KiB
YAML
191 lines
4.5 KiB
YAML
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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/memory-controllers/ti,gpmc.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: Texas Instruments GPMC Memory Controller
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maintainers:
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- Tony Lindgren <tony@atomide.com>
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- Roger Quadros <rogerq@kernel.org>
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description:
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The GPMC is a unified memory controller dedicated for interfacing
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with external memory devices like
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- Asynchronous SRAM-like memories and ASICs
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- Asynchronous, synchronous, and page mode burst NOR flash
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- NAND flash
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- Pseudo-SRAM devices
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properties:
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compatible:
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items:
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- enum:
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- ti,am3352-gpmc
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- ti,am64-gpmc
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- ti,omap2420-gpmc
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- ti,omap2430-gpmc
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- ti,omap3430-gpmc
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- ti,omap4430-gpmc
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reg:
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minItems: 1
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maxItems: 2
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reg-names:
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items:
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- const: cfg
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- const: data
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interrupts:
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maxItems: 1
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clocks:
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maxItems: 1
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description: |
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Functional clock. Used for bus timing calculations and
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GPMC configuration.
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clock-names:
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items:
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- const: fck
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power-domains:
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maxItems: 1
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dmas:
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items:
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- description: DMA channel for GPMC NAND prefetch
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dma-names:
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items:
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- const: rxtx
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"#address-cells": true
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"#size-cells": true
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gpmc,num-cs:
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description: maximum number of supported chip-select lines.
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$ref: /schemas/types.yaml#/definitions/uint32
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gpmc,num-waitpins:
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description: maximum number of supported wait pins.
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$ref: /schemas/types.yaml#/definitions/uint32
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ranges:
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minItems: 1
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description: |
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Must be set up to reflect the memory layout with four
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integer values for each chip-select line in use,
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<cs-number> 0 <physical address of mapping> <size>
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items:
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- description: NAND bank 0
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- description: NOR/SRAM bank 0
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- description: NOR/SRAM bank 1
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'#interrupt-cells':
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const: 2
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interrupt-controller:
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description: |
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The GPMC driver implements an interrupt controller for
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the NAND events "fifoevent" and "termcount" plus the
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rising/falling edges on the GPMC_WAIT pins.
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The interrupt number mapping is as follows
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0 - NAND_fifoevent
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1 - NAND_termcount
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2 - GPMC_WAIT0 pin edge
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3 - GPMC_WAIT1 pin edge, and so on.
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'#gpio-cells':
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const: 2
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gpio-controller:
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description: |
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The GPMC driver implements a GPIO controller for the
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GPMC WAIT pins that can be used as general purpose inputs.
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0 maps to GPMC_WAIT0 pin.
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ti,hwmods:
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description:
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Name of the HWMOD associated with GPMC. This is for legacy
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omap2/3 platforms only.
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$ref: /schemas/types.yaml#/definitions/string
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deprecated: true
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ti,no-idle-on-init:
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description:
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Prevent idling the module at init. This is for legacy omap2/3
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platforms only.
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type: boolean
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deprecated: true
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patternProperties:
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"@[0-7],[a-f0-9]+$":
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type: object
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description: |
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The child device node represents the device connected to the GPMC
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bus. The device can be a NAND chip, SRAM device, NOR device
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or an ASIC.
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$ref: "ti,gpmc-child.yaml"
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required:
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- compatible
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- reg
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- gpmc,num-cs
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- gpmc,num-waitpins
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- "#address-cells"
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- "#size-cells"
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allOf:
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- if:
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properties:
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compatible:
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contains:
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const: ti,am64-gpmc
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then:
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required:
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- reg-names
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- power-domains
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additionalProperties: false
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examples:
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- |
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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#include <dt-bindings/gpio/gpio.h>
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gpmc: memory-controller@50000000 {
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compatible = "ti,am3352-gpmc";
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reg = <0x50000000 0x2000>;
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interrupts = <100>;
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clocks = <&l3s_clkctrl>;
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clock-names = "fck";
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dmas = <&edma 52 0>;
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dma-names = "rxtx";
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gpmc,num-cs = <8>;
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gpmc,num-waitpins = <2>;
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#address-cells = <2>;
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#size-cells = <1>;
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ranges = <0 0 0x08000000 0x10000000>; /* CS0 @addr 0x8000000, size 0x10000000 */
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interrupt-controller;
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#interrupt-cells = <2>;
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gpio-controller;
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#gpio-cells = <2>;
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nand@0,0 {
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compatible = "ti,omap2-nand";
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reg = <0 0 4>;
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interrupt-parent = <&gpmc>;
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interrupts = <0 IRQ_TYPE_NONE>, /* fifoevent */
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<1 IRQ_TYPE_NONE>; /* termcount */
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ti,nand-xfer-type = "prefetch-dma";
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ti,nand-ecc-opt = "bch16";
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ti,elm-id = <&elm>;
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rb-gpios = <&gpmc 0 GPIO_ACTIVE_HIGH>; /* gpmc_wait0 pin */
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};
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};
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