331 lines
10 KiB
YAML
331 lines
10 KiB
YAML
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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/mmc/arasan,sdhci.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: Arasan SDHCI Controller
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maintainers:
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- Adrian Hunter <adrian.hunter@intel.com>
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allOf:
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- $ref: mmc-controller.yaml#
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- if:
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properties:
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compatible:
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contains:
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const: arasan,sdhci-5.1
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then:
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required:
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- phys
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- phy-names
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- if:
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properties:
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compatible:
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contains:
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enum:
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- xlnx,zynqmp-8.9a
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- xlnx,versal-8.9a
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then:
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properties:
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clock-output-names:
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oneOf:
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- items:
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- const: clk_out_sd0
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- const: clk_in_sd0
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- items:
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- const: clk_out_sd1
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- const: clk_in_sd1
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properties:
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compatible:
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oneOf:
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- const: arasan,sdhci-8.9a # generic Arasan SDHCI 8.9a PHY
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- const: arasan,sdhci-4.9a # generic Arasan SDHCI 4.9a PHY
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- const: arasan,sdhci-5.1 # generic Arasan SDHCI 5.1 PHY
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- items:
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- const: rockchip,rk3399-sdhci-5.1 # rk3399 eMMC PHY
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- const: arasan,sdhci-5.1
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description:
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For this device it is strongly suggested to include
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arasan,soc-ctl-syscon.
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- items:
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- const: xlnx,zynqmp-8.9a # ZynqMP SDHCI 8.9a PHY
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- const: arasan,sdhci-8.9a
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description:
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For this device it is strongly suggested to include
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clock-output-names and '#clock-cells'.
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- items:
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- const: xlnx,versal-8.9a # Versal SDHCI 8.9a PHY
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- const: arasan,sdhci-8.9a
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description:
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For this device it is strongly suggested to include
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clock-output-names and '#clock-cells'.
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- items:
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- const: intel,lgm-sdhci-5.1-emmc # Intel LGM eMMC PHY
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- const: arasan,sdhci-5.1
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description:
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For this device it is strongly suggested to include
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arasan,soc-ctl-syscon.
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- items:
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- const: intel,lgm-sdhci-5.1-sdxc # Intel LGM SDXC PHY
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- const: arasan,sdhci-5.1
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description:
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For this device it is strongly suggested to include
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arasan,soc-ctl-syscon.
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- items:
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- const: intel,keembay-sdhci-5.1-emmc # Intel Keem Bay eMMC PHY
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- const: arasan,sdhci-5.1
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description:
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For this device it is strongly suggested to include
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arasan,soc-ctl-syscon.
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- const: intel,keembay-sdhci-5.1-sd # Intel Keem Bay SD controller
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description:
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For this device it is strongly suggested to include
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arasan,soc-ctl-syscon.
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- const: intel,keembay-sdhci-5.1-sdio # Intel Keem Bay SDIO controller
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description:
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For this device it is strongly suggested to include
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arasan,soc-ctl-syscon.
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- items:
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- const: intel,thunderbay-sdhci-5.1 # Intel Thunder Bay eMMC PHY
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- const: arasan,sdhci-5.1
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description:
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For this device it is strongly suggested to include
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clock-output-names and '#clock-cells'.
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reg:
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maxItems: 1
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clocks:
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minItems: 2
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maxItems: 3
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clock-names:
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minItems: 2
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items:
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- const: clk_xin
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- const: clk_ahb
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- const: gate
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interrupts:
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maxItems: 1
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phys:
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maxItems: 1
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phy-names:
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const: phy_arasan
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resets:
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maxItems: 1
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arasan,soc-ctl-syscon:
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$ref: /schemas/types.yaml#/definitions/phandle
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description:
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A phandle to a syscon device (see ../mfd/syscon.txt) used to access
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core corecfg registers. Offsets of registers in this syscon are
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determined based on the main compatible string for the device.
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clock-output-names:
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minItems: 1
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maxItems: 2
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description:
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Name of the card clock which will be exposed by this device.
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'#clock-cells':
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enum: [0, 1]
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description:
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With this property in place we will export one or two clocks
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representing the Card Clock. These clocks are expected to be
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consumed by our PHY.
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xlnx,fails-without-test-cd:
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$ref: /schemas/types.yaml#/definitions/flag
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description:
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When present, the controller doesn't work when the CD line is not
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connected properly, and the line is not connected properly.
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Test mode can be used to force the controller to function.
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xlnx,int-clock-stable-broken:
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$ref: /schemas/types.yaml#/definitions/flag
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description:
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When present, the controller always reports that the internal clock
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is stable even when it is not.
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xlnx,mio-bank:
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$ref: /schemas/types.yaml#/definitions/uint32
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enum: [0, 1, 2]
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default: 0
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description:
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The MIO bank number in which the command and data lines are configured.
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dependencies:
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'#clock-cells': [ clock-output-names ]
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required:
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- compatible
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- reg
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- interrupts
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- clocks
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- clock-names
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unevaluatedProperties: false
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examples:
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- |
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mmc@e0100000 {
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compatible = "arasan,sdhci-8.9a";
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reg = <0xe0100000 0x1000>;
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clock-names = "clk_xin", "clk_ahb";
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clocks = <&clkc 21>, <&clkc 32>;
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interrupt-parent = <&gic>;
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interrupts = <0 24 4>;
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};
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- |
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mmc@e2800000 {
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compatible = "arasan,sdhci-5.1";
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reg = <0xe2800000 0x1000>;
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clock-names = "clk_xin", "clk_ahb";
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clocks = <&cru 8>, <&cru 18>;
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interrupt-parent = <&gic>;
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interrupts = <0 24 4>;
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phys = <&emmc_phy>;
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phy-names = "phy_arasan";
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};
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- |
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#include <dt-bindings/clock/rk3399-cru.h>
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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#include <dt-bindings/interrupt-controller/irq.h>
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mmc@fe330000 {
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compatible = "rockchip,rk3399-sdhci-5.1", "arasan,sdhci-5.1";
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reg = <0xfe330000 0x10000>;
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interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&cru SCLK_EMMC>, <&cru ACLK_EMMC>;
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clock-names = "clk_xin", "clk_ahb";
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arasan,soc-ctl-syscon = <&grf>;
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assigned-clocks = <&cru SCLK_EMMC>;
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assigned-clock-rates = <200000000>;
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clock-output-names = "emmc_cardclock";
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phys = <&emmc_phy>;
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phy-names = "phy_arasan";
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#clock-cells = <0>;
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};
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- |
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mmc@ff160000 {
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compatible = "xlnx,zynqmp-8.9a", "arasan,sdhci-8.9a";
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interrupt-parent = <&gic>;
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interrupts = <0 48 4>;
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reg = <0xff160000 0x1000>;
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clocks = <&clk200>, <&clk200>;
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clock-names = "clk_xin", "clk_ahb";
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clock-output-names = "clk_out_sd0", "clk_in_sd0";
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#clock-cells = <1>;
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clk-phase-sd-hs = <63>, <72>;
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};
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mmc@f1040000 {
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compatible = "xlnx,versal-8.9a", "arasan,sdhci-8.9a";
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interrupt-parent = <&gic>;
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interrupts = <0 126 4>;
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reg = <0xf1040000 0x10000>;
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clocks = <&clk200>, <&clk200>;
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clock-names = "clk_xin", "clk_ahb";
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clock-output-names = "clk_out_sd0", "clk_in_sd0";
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#clock-cells = <1>;
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clk-phase-sd-hs = <132>, <60>;
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};
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- |
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#define LGM_CLK_EMMC5
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#define LGM_CLK_NGI
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#define LGM_GCLK_EMMC
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mmc@ec700000 {
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compatible = "intel,lgm-sdhci-5.1-emmc", "arasan,sdhci-5.1";
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reg = <0xec700000 0x300>;
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interrupt-parent = <&ioapic1>;
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interrupts = <44 1>;
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clocks = <&cgu0 LGM_CLK_EMMC5>, <&cgu0 LGM_CLK_NGI>,
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<&cgu0 LGM_GCLK_EMMC>;
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clock-names = "clk_xin", "clk_ahb", "gate";
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clock-output-names = "emmc_cardclock";
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#clock-cells = <0>;
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phys = <&emmc_phy>;
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phy-names = "phy_arasan";
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arasan,soc-ctl-syscon = <&sysconf>;
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};
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#define LGM_CLK_SDIO
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#define LGM_GCLK_SDXC
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mmc@ec600000 {
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compatible = "intel,lgm-sdhci-5.1-sdxc", "arasan,sdhci-5.1";
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reg = <0xec600000 0x300>;
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interrupt-parent = <&ioapic1>;
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interrupts = <43 1>;
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clocks = <&cgu0 LGM_CLK_SDIO>, <&cgu0 LGM_CLK_NGI>,
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<&cgu0 LGM_GCLK_SDXC>;
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clock-names = "clk_xin", "clk_ahb", "gate";
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clock-output-names = "sdxc_cardclock";
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#clock-cells = <0>;
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phys = <&sdxc_phy>;
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phy-names = "phy_arasan";
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arasan,soc-ctl-syscon = <&sysconf>;
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};
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- |
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#define KEEM_BAY_PSS_AUX_EMMC
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#define KEEM_BAY_PSS_EMMC
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mmc@33000000 {
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compatible = "intel,keembay-sdhci-5.1-emmc", "arasan,sdhci-5.1";
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interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
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reg = <0x33000000 0x300>;
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clock-names = "clk_xin", "clk_ahb";
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clocks = <&scmi_clk KEEM_BAY_PSS_AUX_EMMC>,
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<&scmi_clk KEEM_BAY_PSS_EMMC>;
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phys = <&emmc_phy>;
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phy-names = "phy_arasan";
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assigned-clocks = <&scmi_clk KEEM_BAY_PSS_AUX_EMMC>;
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assigned-clock-rates = <200000000>;
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clock-output-names = "emmc_cardclock";
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#clock-cells = <0>;
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arasan,soc-ctl-syscon = <&mmc_phy_syscon>;
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};
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- |
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#define KEEM_BAY_PSS_AUX_SD0
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#define KEEM_BAY_PSS_SD0
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mmc@31000000 {
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compatible = "intel,keembay-sdhci-5.1-sd";
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interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
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reg = <0x31000000 0x300>;
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clock-names = "clk_xin", "clk_ahb";
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clocks = <&scmi_clk KEEM_BAY_PSS_AUX_SD0>,
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<&scmi_clk KEEM_BAY_PSS_SD0>;
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arasan,soc-ctl-syscon = <&sd0_phy_syscon>;
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};
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- |
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#define EMMC_XIN_CLK
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#define EMMC_AXI_CLK
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#define TBH_PSS_EMMC_RST_N
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mmc@80420000 {
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compatible = "intel,thunderbay-sdhci-5.1", "arasan,sdhci-5.1";
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interrupts = <GIC_SPI 714 IRQ_TYPE_LEVEL_HIGH>;
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reg = <0x80420000 0x400>;
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clocks = <&scmi_clk EMMC_XIN_CLK>,
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<&scmi_clk EMMC_AXI_CLK>;
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clock-names = "clk_xin", "clk_ahb";
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phys = <&emmc_phy>;
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phy-names = "phy_arasan";
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assigned-clocks = <&scmi_clk EMMC_XIN_CLK>;
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clock-output-names = "emmc_cardclock";
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resets = <&rst_pss1 TBH_PSS_EMMC_RST_N>;
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#clock-cells = <0x0>;
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};
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