108 lines
2.7 KiB
YAML
108 lines
2.7 KiB
YAML
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# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/nvmem/nvmem.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: NVMEM (Non Volatile Memory)
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maintainers:
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- Srinivas Kandagatla <srinivas.kandagatla@linaro.org>
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description: |
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This binding is intended to represent the location of hardware
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configuration data stored in NVMEMs like eeprom, efuses and so on.
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On a significant proportion of boards, the manufacturer has stored
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some data on NVMEM, for the OS to be able to retrieve these
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information and act upon it. Obviously, the OS has to know about
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where to retrieve these data from, and where they are stored on the
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storage device.
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properties:
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"#address-cells":
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const: 1
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"#size-cells":
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const: 1
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read-only:
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$ref: /schemas/types.yaml#/definitions/flag
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description:
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Mark the provider as read only.
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wp-gpios:
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description:
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GPIO to which the write-protect pin of the chip is connected.
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The write-protect GPIO is asserted, when it's driven high
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(logical '1') to block the write operation. It's deasserted,
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when it's driven low (logical '0') to allow writing.
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maxItems: 1
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nvmem-layout:
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$ref: /schemas/nvmem/layouts/nvmem-layout.yaml
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description:
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Alternative to the statically defined nvmem cells, this
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container may reference more advanced (dynamic) layout
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parsers.
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patternProperties:
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"@[0-9a-f]+(,[0-7])?$":
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type: object
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properties:
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reg:
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maxItems: 1
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description:
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Offset and size in bytes within the storage device.
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bits:
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$ref: /schemas/types.yaml#/definitions/uint32-array
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items:
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- minimum: 0
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maximum: 7
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description:
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Offset in bit within the address range specified by reg.
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- minimum: 1
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description:
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Size in bit within the address range specified by reg.
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additionalProperties: true
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examples:
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- |
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#include <dt-bindings/gpio/gpio.h>
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qfprom: eeprom@700000 {
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compatible = "qcom,msm8974-qfprom", "qcom,qfprom";
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#address-cells = <1>;
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#size-cells = <1>;
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reg = <0x00700000 0x100000>;
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wp-gpios = <&gpio1 3 GPIO_ACTIVE_HIGH>;
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/* ... */
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/* Data cells */
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tsens_calibration: calib@404 {
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reg = <0x404 0x10>;
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};
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tsens_calibration_bckp: calib_bckp@504 {
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reg = <0x504 0x11>;
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bits = <6 128>;
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};
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pvs_version: pvs-version@6 {
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reg = <0x6 0x2>;
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bits = <7 2>;
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};
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speed_bin: speed-bin@c{
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reg = <0xc 0x1>;
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bits = <2 3>;
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};
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};
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...
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