267 lines
9.8 KiB
YAML
267 lines
9.8 KiB
YAML
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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/pci/snps,dw-pcie-common.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: Synopsys DWC PCIe RP/EP controller
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maintainers:
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- Jingoo Han <jingoohan1@gmail.com>
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- Gustavo Pimentel <gustavo.pimentel@synopsys.com>
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description:
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Generic Synopsys DesignWare PCIe Root Port and Endpoint controller
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properties.
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select: false
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properties:
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reg:
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description:
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DWC PCIe CSR space is normally accessed over the dedicated Data Bus
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Interface - DBI. In accordance with the reference manual the register
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configuration space belongs to the Configuration-Dependent Module (CDM)
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and is split up into several sub-parts Standard PCIe configuration
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space, Port Logic Registers (PL), Shadow Config-space Registers,
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iATU/eDMA registers. The particular sub-space is selected by the
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CDM/ELBI (dbi_cs) and CS2 (dbi_cs2) signals (selector bits). Such
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configuration provides a flexible interface for the system engineers to
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either map the particular space at a desired MMIO address or just leave
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them in a contiguous memory space if pure Native or AXI Bridge DBI access
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is selected. Note the PCIe CFG-space, PL and Shadow registers are
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specific for each activated function, while the rest of the sub-spaces
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are common for all of them (if there are more than one).
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minItems: 2
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maxItems: 6
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reg-names:
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minItems: 2
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maxItems: 6
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interrupts:
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description:
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There are two main sub-blocks which are normally capable of
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generating interrupts. It's System Information Interface and MSI
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interface. While the former one has some common for the Host and
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Endpoint controllers IRQ-signals, the later interface is obviously
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Root Complex specific since it's responsible for the incoming MSI
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messages signalling. The System Information IRQ signals are mainly
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responsible for reporting the generic PCIe hierarchy and Root
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Complex events like VPD IO request, general AER, PME, Hot-plug, link
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bandwidth change, link equalization request, INTx asserted/deasserted
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Message detection, embedded DMA Tx/Rx/Error.
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minItems: 1
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maxItems: 26
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interrupt-names:
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minItems: 1
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maxItems: 26
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clocks:
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description:
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DWC PCIe reference manual explicitly defines a set of the clocks required
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to get the controller working correctly. In general all of them can
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be divided into two groups':' application and core clocks. Note the
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platforms may have some of the clock sources unspecified in case if the
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corresponding domains are fed up from a common clock source.
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minItems: 1
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maxItems: 7
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clock-names:
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minItems: 1
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maxItems: 7
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items:
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oneOf:
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- description:
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Data Bus Interface (DBI) clock. Clock signal for the AXI-bus
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interface of the Configuration-Dependent Module, which is
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basically the set of the controller CSRs.
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const: dbi
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- description:
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Application AXI-bus Master interface clock. Basically this is
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a clock for the controller DMA interface (PCI-to-CPU).
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const: mstr
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- description:
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Application AXI-bus Slave interface clock. This is a clock for
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the CPU-to-PCI memory IO interface.
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const: slv
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- description:
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Controller Core-PCS PIPE interface clock. It's normally
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supplied by an external PCS-PHY.
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const: pipe
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- description:
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Controller Primary clock. It's assumed that all controller input
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signals (except resets) are synchronous to this clock.
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const: core
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- description:
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Auxiliary clock for the controller PMC domain. The controller
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partitioning implies having some parts to operate with this
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clock in some power management states.
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const: aux
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- description:
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Generic reference clock. In case if there are several
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interfaces fed up with a common clock source it's advisable to
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define it with this name (for instance pipe, core and aux can
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be connected to a single source of the periodic signal).
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const: ref
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- description:
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Clock for the PHY registers interface. Originally this is
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a PHY-viewport-based interface, but some platform may have
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specifically designed one.
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const: phy_reg
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- description:
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Vendor-specific clock names. Consider using the generic names
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above for new bindings.
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oneOf:
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- description: See native 'dbi' clock for details
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enum: [ pcie, pcie_apb_sys, aclk_dbi ]
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- description: See native 'mstr/slv' clock for details
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enum: [ pcie_bus, pcie_inbound_axi, pcie_aclk, aclk_mst, aclk_slv ]
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- description: See native 'pipe' clock for details
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enum: [ pcie_phy, pcie_phy_ref, link ]
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- description: See native 'aux' clock for details
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enum: [ pcie_aux ]
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- description: See native 'ref' clock for details.
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enum: [ gio ]
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- description: See nativs 'phy_reg' clock for details
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enum: [ pcie_apb_phy, pclk ]
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resets:
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description:
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DWC PCIe reference manual explicitly defines a set of the reset
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signals required to be de-asserted to properly activate the controller
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sub-parts. All of these signals can be divided into two sub-groups':'
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application and core resets with respect to the main sub-domains they
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are supposed to reset. Note the platforms may have some of these signals
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unspecified in case if they are automatically handled or aggregated into
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a comprehensive control module.
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minItems: 1
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maxItems: 10
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reset-names:
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minItems: 1
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maxItems: 10
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items:
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oneOf:
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- description: Data Bus Interface (DBI) domain reset
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const: dbi
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- description: AXI-bus Master interface reset
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const: mstr
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- description: AXI-bus Slave interface reset
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const: slv
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- description: Application-dependent interface reset
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const: app
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- description: Controller Non-sticky CSR flags reset
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const: non-sticky
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- description: Controller sticky CSR flags reset
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const: sticky
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- description: PIPE-interface (Core-PCS) logic reset
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const: pipe
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- description:
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Controller primary reset (resets everything except PMC module)
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const: core
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- description: PCS/PHY block reset
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const: phy
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- description: PMC hot reset signal
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const: hot
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- description: Cold reset signal
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const: pwr
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- description:
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Vendor-specific reset names. Consider using the generic names
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above for new bindings.
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oneOf:
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- description: See native 'app' reset for details
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enum: [ apps, gio, apb ]
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- description: See native 'phy' reset for details
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enum: [ pciephy, link ]
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- description: See native 'pwr' reset for details
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enum: [ turnoff ]
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phys:
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description:
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There can be up to the number of possible lanes PHYs specified placed in
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the phandle array in the line-based order. Obviously each the specified
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PHYs are supposed to be able to work in the PCIe mode with a speed
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implied by the DWC PCIe controller they are attached to.
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minItems: 1
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maxItems: 16
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phy-names:
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minItems: 1
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maxItems: 16
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oneOf:
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- description: Generic PHY names
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items:
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pattern: '^pcie[0-9]+$'
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- description:
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Vendor-specific PHY names. Consider using the generic
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names above for new bindings.
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items:
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oneOf:
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- pattern: '^pcie(-?phy[0-9]*)?$'
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- pattern: '^p2u-[0-7]$'
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reset-gpio:
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deprecated: true
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description:
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Reference to the GPIO-controlled PERST# signal. It is used to reset all
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the peripheral devices available on the PCIe bus.
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maxItems: 1
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reset-gpios:
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description:
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Reference to the GPIO-controlled PERST# signal. It is used to reset all
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the peripheral devices available on the PCIe bus.
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maxItems: 1
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max-link-speed:
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maximum: 5
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num-lanes:
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description:
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Number of PCIe link lanes to use. Can be omitted if the already brought
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up link is supposed to be preserved.
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maximum: 16
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num-ob-windows:
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$ref: /schemas/types.yaml#/definitions/uint32
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deprecated: true
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description:
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Number of outbound address translation windows. This parameter can be
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auto-detected based on the iATU memory writability. So there is no
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point in having a dedicated DT-property for it.
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maximum: 256
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num-ib-windows:
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$ref: /schemas/types.yaml#/definitions/uint32
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deprecated: true
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description:
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Number of inbound address translation windows. In the same way as
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for the outbound AT windows, this parameter can be auto-detected based
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on the iATU memory writability. There is no point having a dedicated
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DT-property for it either.
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maximum: 256
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num-viewport:
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$ref: /schemas/types.yaml#/definitions/uint32
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deprecated: true
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description:
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Number of outbound view ports configured in hardware. It's the same as
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the number of outbound AT windows.
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maximum: 256
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snps,enable-cdm-check:
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$ref: /schemas/types.yaml#/definitions/flag
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description:
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Enable automatic checking of CDM (Configuration Dependent Module)
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registers for data corruption. CDM registers include standard PCIe
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configuration space registers, Port Logic registers, DMA and iATU
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registers. This feature has been available since DWC PCIe v4.80a.
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dma-coherent: true
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additionalProperties: true
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...
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