112 lines
3.0 KiB
YAML
112 lines
3.0 KiB
YAML
|
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
|
||
|
|
%YAML 1.2
|
||
|
|
---
|
||
|
|
$id: http://devicetree.org/schemas/pci/toshiba,visconti-pcie.yaml#
|
||
|
|
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||
|
|
|
||
|
|
title: Toshiba Visconti5 SoC PCIe Host Controller
|
||
|
|
|
||
|
|
maintainers:
|
||
|
|
- Nobuhiro Iwamatsu <nobuhiro1.iwamatsu@toshiba.co.jp>
|
||
|
|
|
||
|
|
description:
|
||
|
|
Toshiba Visconti5 SoC PCIe host controller is based on the Synopsys DesignWare PCIe IP.
|
||
|
|
|
||
|
|
allOf:
|
||
|
|
- $ref: /schemas/pci/snps,dw-pcie.yaml#
|
||
|
|
|
||
|
|
properties:
|
||
|
|
compatible:
|
||
|
|
const: toshiba,visconti-pcie
|
||
|
|
|
||
|
|
reg:
|
||
|
|
items:
|
||
|
|
- description: Data Bus Interface (DBI) registers.
|
||
|
|
- description: PCIe configuration space region.
|
||
|
|
- description: Visconti specific additional registers.
|
||
|
|
- description: Visconti specific SMU registers
|
||
|
|
- description: Visconti specific memory protection unit registers (MPU)
|
||
|
|
|
||
|
|
reg-names:
|
||
|
|
items:
|
||
|
|
- const: dbi
|
||
|
|
- const: config
|
||
|
|
- const: ulreg
|
||
|
|
- const: smu
|
||
|
|
- const: mpu
|
||
|
|
|
||
|
|
interrupts:
|
||
|
|
maxItems: 2
|
||
|
|
|
||
|
|
clocks:
|
||
|
|
items:
|
||
|
|
- description: PCIe reference clock
|
||
|
|
- description: PCIe system clock
|
||
|
|
- description: Auxiliary clock
|
||
|
|
|
||
|
|
clock-names:
|
||
|
|
items:
|
||
|
|
- const: ref
|
||
|
|
- const: core
|
||
|
|
- const: aux
|
||
|
|
|
||
|
|
num-lanes:
|
||
|
|
const: 2
|
||
|
|
|
||
|
|
required:
|
||
|
|
- reg
|
||
|
|
- reg-names
|
||
|
|
- interrupts
|
||
|
|
- "#interrupt-cells"
|
||
|
|
- interrupt-map
|
||
|
|
- interrupt-map-mask
|
||
|
|
- num-lanes
|
||
|
|
- clocks
|
||
|
|
- clock-names
|
||
|
|
- max-link-speed
|
||
|
|
|
||
|
|
unevaluatedProperties: false
|
||
|
|
|
||
|
|
examples:
|
||
|
|
- |
|
||
|
|
#include <dt-bindings/interrupt-controller/irq.h>
|
||
|
|
#include <dt-bindings/interrupt-controller/arm-gic.h>
|
||
|
|
|
||
|
|
soc {
|
||
|
|
#address-cells = <2>;
|
||
|
|
#size-cells = <2>;
|
||
|
|
|
||
|
|
pcie: pcie@28400000 {
|
||
|
|
compatible = "toshiba,visconti-pcie";
|
||
|
|
reg = <0x0 0x28400000 0x0 0x00400000>,
|
||
|
|
<0x0 0x70000000 0x0 0x10000000>,
|
||
|
|
<0x0 0x28050000 0x0 0x00010000>,
|
||
|
|
<0x0 0x24200000 0x0 0x00002000>,
|
||
|
|
<0x0 0x24162000 0x0 0x00001000>;
|
||
|
|
reg-names = "dbi", "config", "ulreg", "smu", "mpu";
|
||
|
|
device_type = "pci";
|
||
|
|
bus-range = <0x00 0xff>;
|
||
|
|
num-lanes = <2>;
|
||
|
|
num-viewport = <8>;
|
||
|
|
|
||
|
|
#address-cells = <3>;
|
||
|
|
#size-cells = <2>;
|
||
|
|
#interrupt-cells = <1>;
|
||
|
|
ranges = <0x81000000 0 0x40000000 0 0x40000000 0 0x00010000>,
|
||
|
|
<0x82000000 0 0x50000000 0 0x50000000 0 0x20000000>;
|
||
|
|
interrupts = <GIC_SPI 211 IRQ_TYPE_LEVEL_HIGH>,
|
||
|
|
<GIC_SPI 215 IRQ_TYPE_LEVEL_HIGH>;
|
||
|
|
interrupt-names = "msi", "intr";
|
||
|
|
interrupt-map-mask = <0 0 0 7>;
|
||
|
|
interrupt-map =
|
||
|
|
<0 0 0 1 &gic GIC_SPI 215 IRQ_TYPE_LEVEL_HIGH
|
||
|
|
0 0 0 2 &gic GIC_SPI 215 IRQ_TYPE_LEVEL_HIGH
|
||
|
|
0 0 0 3 &gic GIC_SPI 215 IRQ_TYPE_LEVEL_HIGH
|
||
|
|
0 0 0 4 &gic GIC_SPI 215 IRQ_TYPE_LEVEL_HIGH>;
|
||
|
|
clocks = <&extclk100mhz>, <&clk600mhz>, <&clk25mhz>;
|
||
|
|
clock-names = "ref", "core", "aux";
|
||
|
|
max-link-speed = <2>;
|
||
|
|
};
|
||
|
|
};
|
||
|
|
...
|