300 lines
6.7 KiB
YAML
300 lines
6.7 KiB
YAML
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# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/phy/qcom,ipq8074-qmp-pcie-phy.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: Qualcomm QMP PHY controller (PCIe, IPQ8074)
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maintainers:
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- Vinod Koul <vkoul@kernel.org>
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description:
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QMP PHY controller supports physical layer functionality for a number of
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controllers on Qualcomm chipsets, such as, PCIe, UFS, and USB.
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Note that these bindings are for SoCs up to SC8180X. For newer SoCs, see
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qcom,sc8280xp-qmp-pcie-phy.yaml.
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properties:
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compatible:
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enum:
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- qcom,ipq6018-qmp-pcie-phy
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- qcom,ipq8074-qmp-gen3-pcie-phy
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- qcom,ipq8074-qmp-pcie-phy
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- qcom,msm8998-qmp-pcie-phy
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- qcom,sc8180x-qmp-pcie-phy
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- qcom,sdm845-qhp-pcie-phy
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- qcom,sdm845-qmp-pcie-phy
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- qcom,sdx55-qmp-pcie-phy
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- qcom,sm8250-qmp-gen3x1-pcie-phy
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- qcom,sm8250-qmp-gen3x2-pcie-phy
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- qcom,sm8250-qmp-modem-pcie-phy
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- qcom,sm8450-qmp-gen3x1-pcie-phy
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- qcom,sm8450-qmp-gen4x2-pcie-phy
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reg:
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items:
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- description: serdes
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"#address-cells":
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enum: [ 1, 2 ]
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"#size-cells":
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enum: [ 1, 2 ]
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ranges: true
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clocks:
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minItems: 2
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maxItems: 4
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clock-names:
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minItems: 2
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maxItems: 4
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resets:
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minItems: 1
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maxItems: 2
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reset-names:
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minItems: 1
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maxItems: 2
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vdda-phy-supply: true
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vdda-pll-supply: true
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vddp-ref-clk-supply: true
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patternProperties:
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"^phy@[0-9a-f]+$":
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type: object
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description: single PHY-provider child node
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properties:
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reg:
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minItems: 3
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maxItems: 6
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clocks:
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items:
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- description: PIPE clock
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clock-names:
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deprecated: true
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items:
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- const: pipe0
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"#clock-cells":
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const: 0
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clock-output-names:
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maxItems: 1
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"#phy-cells":
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const: 0
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required:
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- reg
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- clocks
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- "#clock-cells"
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- clock-output-names
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- "#phy-cells"
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additionalProperties: false
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required:
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- compatible
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- reg
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- "#address-cells"
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- "#size-cells"
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- ranges
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- clocks
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- clock-names
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- resets
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- reset-names
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additionalProperties: false
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allOf:
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- if:
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properties:
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compatible:
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contains:
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enum:
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- qcom,msm8998-qmp-pcie-phy
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then:
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properties:
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clocks:
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maxItems: 3
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clock-names:
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items:
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- const: aux
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- const: cfg_ahb
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- const: ref
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resets:
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maxItems: 2
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reset-names:
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items:
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- const: phy
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- const: common
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required:
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- vdda-phy-supply
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- vdda-pll-supply
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- if:
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properties:
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compatible:
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contains:
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enum:
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- qcom,ipq6018-qmp-pcie-phy
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- qcom,ipq8074-qmp-gen3-pcie-phy
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- qcom,ipq8074-qmp-pcie-phy
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then:
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properties:
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clocks:
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maxItems: 2
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clock-names:
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items:
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- const: aux
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- const: cfg_ahb
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resets:
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maxItems: 2
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reset-names:
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items:
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- const: phy
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- const: common
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- if:
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properties:
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compatible:
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contains:
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enum:
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- qcom,sc8180x-qmp-pcie-phy
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- qcom,sdm845-qhp-pcie-phy
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- qcom,sdm845-qmp-pcie-phy
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- qcom,sdx55-qmp-pcie-phy
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- qcom,sm8250-qmp-gen3x1-pcie-phy
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- qcom,sm8250-qmp-gen3x2-pcie-phy
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- qcom,sm8250-qmp-modem-pcie-phy
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- qcom,sm8450-qmp-gen3x1-pcie-phy
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- qcom,sm8450-qmp-gen4x2-pcie-phy
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then:
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properties:
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clocks:
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maxItems: 4
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clock-names:
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items:
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- const: aux
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- const: cfg_ahb
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- const: ref
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- const: refgen
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resets:
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maxItems: 1
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reset-names:
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items:
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- const: phy
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required:
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- vdda-phy-supply
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- vdda-pll-supply
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- if:
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properties:
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compatible:
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contains:
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enum:
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- qcom,sm8250-qmp-gen3x2-pcie-phy
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- qcom,sm8250-qmp-modem-pcie-phy
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- qcom,sm8450-qmp-gen4x2-pcie-phy
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then:
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patternProperties:
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"^phy@[0-9a-f]+$":
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properties:
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reg:
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items:
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- description: TX lane 1
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- description: RX lane 1
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- description: PCS
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- description: TX lane 2
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- description: RX lane 2
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- description: PCS_MISC
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- if:
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properties:
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compatible:
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contains:
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enum:
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- qcom,sc8180x-qmp-pcie-phy
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- qcom,sdm845-qmp-pcie-phy
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- qcom,sdx55-qmp-pcie-phy
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- qcom,sm8250-qmp-gen3x1-pcie-phy
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- qcom,sm8450-qmp-gen3x1-pcie-phy
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then:
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patternProperties:
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"^phy@[0-9a-f]+$":
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properties:
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reg:
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items:
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- description: TX
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- description: RX
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- description: PCS
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- description: PCS_MISC
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- if:
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properties:
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compatible:
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contains:
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enum:
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- qcom,ipq6018-qmp-pcie-phy
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- qcom,ipq8074-qmp-pcie-phy
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- qcom,msm8998-qmp-pcie-phy
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- qcom,sdm845-qhp-pcie-phy
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then:
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patternProperties:
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"^phy@[0-9a-f]+$":
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properties:
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reg:
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items:
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- description: TX
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- description: RX
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- description: PCS
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examples:
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- |
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#include <dt-bindings/clock/qcom,gcc-sm8250.h>
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phy-wrapper@1c0e000 {
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compatible = "qcom,sm8250-qmp-gen3x2-pcie-phy";
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reg = <0x01c0e000 0x1c0>;
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#address-cells = <1>;
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#size-cells = <1>;
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ranges = <0x0 0x01c0e000 0x1000>;
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clocks = <&gcc GCC_PCIE_PHY_AUX_CLK>,
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<&gcc GCC_PCIE_1_CFG_AHB_CLK>,
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<&gcc GCC_PCIE_WIGIG_CLKREF_EN>,
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<&gcc GCC_PCIE1_PHY_REFGEN_CLK>;
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clock-names = "aux", "cfg_ahb", "ref", "refgen";
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resets = <&gcc GCC_PCIE_1_PHY_BCR>;
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reset-names = "phy";
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vdda-phy-supply = <&vreg_l10c_0p88>;
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vdda-pll-supply = <&vreg_l6b_1p2>;
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phy@200 {
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reg = <0x200 0x170>,
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<0x400 0x200>,
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<0xa00 0x1f0>,
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<0x600 0x170>,
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<0x800 0x200>,
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<0xe00 0xf4>;
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clocks = <&gcc GCC_PCIE_1_PIPE_CLK>;
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#clock-cells = <0>;
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clock-output-names = "pcie_1_pipe_clk";
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#phy-cells = <0>;
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};
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};
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