135 lines
3.9 KiB
YAML
135 lines
3.9 KiB
YAML
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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/pinctrl/qcom,ipq5332-tlmm.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: Qualcomm IPQ5332 TLMM pin controller
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maintainers:
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- Bjorn Andersson <andersson@kernel.org>
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- Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
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description: |
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Top Level Mode Multiplexer pin controller in Qualcomm IPQ5332 SoC.
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allOf:
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- $ref: /schemas/pinctrl/qcom,tlmm-common.yaml#
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properties:
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compatible:
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const: qcom,ipq5332-tlmm
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reg:
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maxItems: 1
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interrupts:
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maxItems: 1
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interrupt-controller: true
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"#interrupt-cells": true
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gpio-controller: true
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"#gpio-cells": true
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gpio-ranges: true
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wakeup-parent: true
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gpio-reserved-ranges:
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minItems: 1
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maxItems: 27
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gpio-line-names:
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maxItems: 53
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patternProperties:
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"-state$":
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oneOf:
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- $ref: "#/$defs/qcom-ipq5332-tlmm-state"
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- patternProperties:
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"-pins$":
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$ref: "#/$defs/qcom-ipq5332-tlmm-state"
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additionalProperties: false
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$defs:
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qcom-ipq5332-tlmm-state:
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type: object
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description:
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Pinctrl node's client devices use subnodes for desired pin configuration.
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Client device subnodes use below standard properties.
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$ref: qcom,tlmm-common.yaml#/$defs/qcom-tlmm-state
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properties:
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pins:
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description:
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List of gpio pins affected by the properties specified in this
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subnode.
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items:
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pattern: "^gpio([0-9]|[1-4][0-9]|5[0-2])$"
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minItems: 1
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maxItems: 36
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function:
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description:
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Specify the alternative function to be configured for the specified
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pins.
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enum: [ atest_char, atest_char0, atest_char1, atest_char2, atest_char3,
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atest_tic, audio_pri, audio_pri0, audio_pri1, audio_sec,
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audio_sec0, audio_sec1, blsp0_i2c, blsp0_spi, blsp0_uart0,
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blsp0_uart1, blsp1_i2c0, blsp1_i2c1, blsp1_spi0, blsp1_spi1,
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blsp1_uart0, blsp1_uart1, blsp1_uart2, blsp2_i2c0, blsp2_i2c1,
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blsp2_spi, blsp2_spi0, blsp2_spi1, core_voltage, cri_trng0,
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cri_trng1, cri_trng2, cri_trng3, cxc_clk, cxc_data, dbg_out,
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gcc_plltest, gcc_tlmm, gpio, lock_det, mac0, mac1, mdc0, mdc1,
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mdio0, mdio1, pc, pcie0_clk, pcie0_wake, pcie1_clk, pcie1_wake,
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pcie2_clk, pcie2_wake, pll_test, prng_rosc0, prng_rosc1,
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prng_rosc2, prng_rosc3, pta, pwm0, pwm1, pwm2, pwm3,
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qdss_cti_trig_in_a0, qdss_cti_trig_in_a1, qdss_cti_trig_in_b0,
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qdss_cti_trig_in_b1, qdss_cti_trig_out_a0,
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qdss_cti_trig_out_a1, qdss_cti_trig_out_b0,
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qdss_cti_trig_out_b1, qdss_traceclk_a, qdss_traceclk_b,
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qdss_tracectl_a, qdss_tracectl_b, qdss_tracedata_a,
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qdss_tracedata_b, qspi_data, qspi_clk, qspi_cs, resout, rx0,
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rx1, sdc_data, sdc_clk, sdc_cmd, tsens_max, wci_txd, wci_rxd,
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wsi_clk, wsi_clk3, wsi_data, wsi_data3, wsis_reset, xfem ]
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bias-pull-down: true
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bias-pull-up: true
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bias-disable: true
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drive-strength: true
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input-enable: true
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output-high: true
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output-low: true
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required:
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- pins
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additionalProperties: false
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required:
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- compatible
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- reg
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additionalProperties: false
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examples:
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- |
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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tlmm: pinctrl@1000000 {
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compatible = "qcom,ipq5332-tlmm";
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reg = <0x01000000 0x300000>;
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gpio-controller;
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#gpio-cells = <0x2>;
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gpio-ranges = <&tlmm 0 0 53>;
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interrupts = <GIC_SPI 249 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-controller;
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#interrupt-cells = <0x2>;
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serial0-state {
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pins = "gpio18", "gpio19";
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function = "blsp0_uart0";
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drive-strength = <8>;
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bias-pull-up;
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};
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};
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