137 lines
4.4 KiB
YAML
137 lines
4.4 KiB
YAML
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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/pinctrl/qcom,sdx55-pinctrl.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: Qualcomm Technologies, Inc. SDX55 TLMM block
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maintainers:
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- Vinod Koul <vkoul@kernel.org>
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description:
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Top Level Mode Multiplexer pin controller in Qualcomm SDX55 SoC.
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properties:
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compatible:
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const: qcom,sdx55-pinctrl
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reg:
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description: Specifies the base address and size of the TLMM register space
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maxItems: 1
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interrupts:
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maxItems: 1
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interrupt-controller: true
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"#interrupt-cells": true
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gpio-controller: true
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"#gpio-cells": true
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gpio-ranges: true
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gpio-reserved-ranges:
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maxItems: 1
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patternProperties:
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"-state$":
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oneOf:
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- $ref: "#/$defs/qcom-sdx55-tlmm-state"
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- patternProperties:
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"-pins$":
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$ref: "#/$defs/qcom-sdx55-tlmm-state"
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additionalProperties: false
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$defs:
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qcom-sdx55-tlmm-state:
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type: object
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description:
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Pinctrl node's client devices use subnodes for desired pin configuration.
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Client device subnodes use below standard properties.
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$ref: qcom,tlmm-common.yaml#/$defs/qcom-tlmm-state
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properties:
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pins:
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description:
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List of gpio pins affected by the properties specified in this subnode.
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items:
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oneOf:
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- pattern: "^gpio([0-9]|[1-9][0-9]|10[0-7])$"
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- enum: [ sdc1_clk, sdc1_cmd, sdc1_data, sdc2_clk, sdc2_cmd, sdc2_data ]
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minItems: 1
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maxItems: 36
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function:
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description:
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Specify the alternative function to be configured for the specified
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pins. Functions are only valid for gpio pins.
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enum: [ adsp_ext, atest, audio_ref, bimc_dte0, bimc_dte1, blsp_i2c1,
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blsp_i2c2, blsp_i2c3, blsp_i2c4, blsp_spi1, blsp_spi2,
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blsp_spi3, blsp_spi4, blsp_uart1, blsp_uart2, blsp_uart3,
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blsp_uart4, char_exec, coex_uart, coex_uart2, cri_trng,
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cri_trng0, cri_trng1, dbg_out, ddr_bist, ddr_pxi0,
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ebi0_wrcdc, ebi2_a, ebi2_lcd, emac_gcc0, emac_gcc1,
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emac_pps0, emac_pps1, ext_dbg, gcc_gp1, gcc_gp2, gcc_gp3,
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gcc_plltest, gpio, i2s_mclk, jitter_bist, ldo_en, ldo_update,
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mgpi_clk, m_voc, native_char, native_char0, native_char1,
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native_char2, native_char3, native_tsens, native_tsense,
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nav_gpio, pa_indicator, pcie_clkreq, pci_e, pll_bist, pll_ref,
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pll_test, pri_mi2s, prng_rosc, qdss_cti, qdss_gpio,
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qdss_gpio0, qdss_gpio1, qdss_gpio2, qdss_gpio3, qdss_gpio4,
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qdss_gpio5, qdss_gpio6, qdss_gpio7, qdss_gpio8, qdss_gpio9,
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qdss_gpio10, qdss_gpio11, qdss_gpio12, qdss_gpio13,
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qdss_gpio14, qdss_gpio15, qdss_stm0, qdss_stm1, qdss_stm2,
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qdss_stm3, qdss_stm4, qdss_stm5, qdss_stm6, qdss_stm7,
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qdss_stm8, qdss_stm9, qdss_stm10, qdss_stm11, qdss_stm12,
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qdss_stm13, qdss_stm14, qdss_stm15, qdss_stm16, qdss_stm17,
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qdss_stm18, qdss_stm19, qdss_stm20, qdss_stm21, qdss_stm22,
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qdss_stm23, qdss_stm24, qdss_stm25, qdss_stm26, qdss_stm27,
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qdss_stm28, qdss_stm29, qdss_stm30, qdss_stm31, qlink0_en,
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qlink0_req, qlink0_wmss, qlink1_en, qlink1_req, qlink1_wmss,
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spmi_coex, sec_mi2s, spmi_vgi, tgu_ch0, uim1_clk, uim1_data,
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uim1_present, uim1_reset, uim2_clk, uim2_data, uim2_present,
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uim2_reset, usb2phy_ac, vsense_trigger ]
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bias-pull-down: true
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bias-pull-up: true
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bias-disable: true
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drive-strength: true
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output-high: true
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output-low: true
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required:
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- pins
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additionalProperties: false
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allOf:
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- $ref: /schemas/pinctrl/qcom,tlmm-common.yaml#
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required:
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- compatible
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- reg
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additionalProperties: false
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examples:
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- |
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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tlmm: pinctrl@1f00000 {
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compatible = "qcom,sdx55-pinctrl";
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reg = <0x0f100000 0x300000>;
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gpio-controller;
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#gpio-cells = <2>;
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gpio-ranges = <&tlmm 0 0 108>;
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interrupt-controller;
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#interrupt-cells = <2>;
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interrupts = <GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH>;
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serial-state {
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pins = "gpio8", "gpio9";
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function = "blsp_uart3";
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drive-strength = <8>;
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bias-disable;
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};
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};
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...
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