84 lines
2.7 KiB
YAML
84 lines
2.7 KiB
YAML
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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/pwm/microchip,corepwm.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: Microchip IP corePWM controller
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maintainers:
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- Conor Dooley <conor.dooley@microchip.com>
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description: |
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corePWM is an 16 channel pulse width modulator FPGA IP
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https://www.microsemi.com/existing-parts/parts/152118
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allOf:
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- $ref: pwm.yaml#
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properties:
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compatible:
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items:
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- const: microchip,corepwm-rtl-v4
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reg:
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maxItems: 1
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clocks:
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maxItems: 1
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"#pwm-cells":
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enum: [2, 3]
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description:
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The only flag supported by the controller is PWM_POLARITY_INVERTED.
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microchip,sync-update-mask:
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description: |
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Depending on how the IP is instantiated, there are two modes of operation.
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In synchronous mode, all channels are updated at the beginning of the PWM period,
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and in asynchronous mode updates happen as the control registers are written.
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A 16 bit wide "SHADOW_REG_EN" parameter of the IP core controls whether synchronous
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mode is possible for each channel, and is set by the bitstream programmed to the
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FPGA. If the IP core is instantiated with SHADOW_REG_ENx=1, both registers that
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control the duty cycle for channel x have a second "shadow"/buffer reg synthesised.
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At runtime a bit wide register exposed to APB can be used to toggle on/off
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synchronised mode for all channels it has been synthesised for.
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Each bit of "microchip,sync-update-mask" corresponds to a PWM channel & represents
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whether synchronous mode is possible for the PWM channel.
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$ref: /schemas/types.yaml#/definitions/uint32
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default: 0
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microchip,dac-mode-mask:
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description: |
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Optional, per-channel Low Ripple DAC mode is possible on this IP core. It creates
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a minimum period pulse train whose High/Low average is that of the chosen duty
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cycle. This "DAC" will have far better bandwidth and ripple performance than the
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standard PWM algorithm can achieve. A 16 bit DAC_MODE module parameter of the IP
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core, set at instantiation and by the bitstream programmed to the FPGA, determines
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whether a given channel operates in regular PWM or DAC mode.
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Each bit corresponds to a PWM channel & represents whether DAC mode is enabled
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for that channel.
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$ref: /schemas/types.yaml#/definitions/uint32
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default: 0
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required:
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- compatible
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- reg
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- clocks
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additionalProperties: false
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examples:
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- |
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pwm@41000000 {
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compatible = "microchip,corepwm-rtl-v4";
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microchip,sync-update-mask = /bits/ 32 <0>;
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clocks = <&clkcfg 30>;
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reg = <0x41000000 0xF0>;
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#pwm-cells = <2>;
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};
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