119 lines
3.2 KiB
YAML
119 lines
3.2 KiB
YAML
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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/soc/imx/fsl,imx8mp-media-blk-ctrl.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: NXP i.MX8MP Media Block Control
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maintainers:
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- Paul Elder <paul.elder@ideasonboard.com>
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description:
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The i.MX8MP Media Block Control (MEDIA BLK_CTRL) is a top-level peripheral
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providing access to the NoC and ensuring proper power sequencing of the
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peripherals within the MEDIAMIX domain.
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properties:
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compatible:
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items:
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- const: fsl,imx8mp-media-blk-ctrl
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- const: syscon
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reg:
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maxItems: 1
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'#power-domain-cells':
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const: 1
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power-domains:
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maxItems: 10
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power-domain-names:
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items:
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- const: bus
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- const: mipi-dsi1
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- const: mipi-csi1
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- const: lcdif1
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- const: isi
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- const: mipi-csi2
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- const: lcdif2
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- const: isp
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- const: dwe
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- const: mipi-dsi2
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clocks:
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items:
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- description: The APB clock
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- description: The AXI clock
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- description: The pixel clock for the first CSI2 receiver (aclk)
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- description: The pixel clock for the second CSI2 receiver (aclk)
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- description: The pixel clock for the first LCDIF (pix_clk)
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- description: The pixel clock for the second LCDIF (pix_clk)
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- description: The core clock for the ISP (clk)
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- description: The MIPI-PHY reference clock used by DSI
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clock-names:
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items:
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- const: apb
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- const: axi
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- const: cam1
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- const: cam2
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- const: disp1
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- const: disp2
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- const: isp
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- const: phy
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interconnects:
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maxItems: 8
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interconnect-names:
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items:
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- const: lcdif-rd
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- const: lcdif-wr
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- const: isi0
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- const: isi1
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- const: isi2
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- const: isp0
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- const: isp1
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- const: dwe
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required:
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- compatible
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- reg
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- '#power-domain-cells'
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- power-domains
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- power-domain-names
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- clocks
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- clock-names
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additionalProperties: false
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examples:
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- |
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#include <dt-bindings/clock/imx8mp-clock.h>
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#include <dt-bindings/power/imx8mp-power.h>
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media_blk_ctl: blk-ctl@32ec0000 {
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compatible = "fsl,imx8mp-media-blk-ctrl", "syscon";
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reg = <0x32ec0000 0x138>;
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power-domains = <&mediamix_pd>, <&mipi_phy1_pd>, <&mipi_phy1_pd>,
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<&mediamix_pd>, <&mediamix_pd>, <&mipi_phy2_pd>,
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<&mediamix_pd>, <&ispdwp_pd>, <&ispdwp_pd>,
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<&mipi_phy2_pd>;
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power-domain-names = "bus", "mipi-dsi1", "mipi-csi1", "lcdif1", "isi",
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"mipi-csi2", "lcdif2", "isp", "dwe", "mipi-dsi2";
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clocks = <&clk IMX8MP_CLK_MEDIA_APB_ROOT>,
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<&clk IMX8MP_CLK_MEDIA_AXI_ROOT>,
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<&clk IMX8MP_CLK_MEDIA_CAM1_PIX_ROOT>,
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<&clk IMX8MP_CLK_MEDIA_CAM2_PIX_ROOT>,
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<&clk IMX8MP_CLK_MEDIA_DISP1_PIX_ROOT>,
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<&clk IMX8MP_CLK_MEDIA_DISP2_PIX_ROOT>,
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<&clk IMX8MP_CLK_MEDIA_ISP_ROOT>,
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<&clk IMX8MP_CLK_MEDIA_MIPI_PHY1_REF_ROOT>;
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clock-names = "apb", "axi", "cam1", "cam2", "disp1", "disp2",
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"isp", "phy";
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#power-domain-cells = <1>;
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};
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...
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