133 lines
3.5 KiB
YAML
133 lines
3.5 KiB
YAML
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# SPDX-License-Identifier: GPL-2.0 OR BSD-2-Clause
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/soc/qcom/qcom,gsbi.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: Qualcomm General Serial Bus Interface (GSBI)
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maintainers:
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- Andy Gross <agross@kernel.org>
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- Bjorn Andersson <bjorn.andersson@linaro.org>
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- Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
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description:
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The GSBI controller is modeled as a node with zero or more child nodes, each
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representing a serial sub-node device that is mux'd as part of the GSBI
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configuration settings. The mode setting will govern the input/output mode
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of the 4 GSBI IOs.
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A GSBI controller node can contain 0 or more child nodes representing serial
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devices. These serial devices can be a QCOM UART, I2C controller, spi
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controller, or some combination of aforementioned devices.
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properties:
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compatible:
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const: qcom,gsbi-v1.0.0
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'#address-cells':
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const: 1
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cell-index:
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$ref: /schemas/types.yaml#/definitions/uint32
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description:
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The GSBI index.
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clocks:
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maxItems: 1
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clock-names:
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const: iface
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qcom,crci:
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$ref: /schemas/types.yaml#/definitions/uint32
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description:
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CRCI MUX value for QUP CRCI ports. Please reference
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include/dt-bindings/soc/qcom,gsbi.h for valid CRCI mux values.
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qcom,mode:
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$ref: /schemas/types.yaml#/definitions/uint32
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description:
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MUX value for configuration of the serial interface. Please reference
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include/dt-bindings/soc/qcom,gsbi.h for valid mux values.
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'#size-cells':
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const: 1
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syscon-tcsr:
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$ref: /schemas/types.yaml#/definitions/phandle
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description:
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Phandle of TCSR syscon node.Required if child uses dma.
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ranges: true
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reg:
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maxItems: 1
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patternProperties:
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"spi@[0-9a-f]+$":
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type: object
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$ref: /schemas/spi/qcom,spi-qup.yaml#
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"i2c@[0-9a-f]+$":
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type: object
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$ref: /schemas/i2c/qcom,i2c-qup.yaml#
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"serial@[0-9a-f]+$":
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type: object
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$ref: /schemas/serial/qcom,msm-uartdm.yaml#
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required:
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- compatible
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- cell-index
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- clocks
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- clock-names
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- qcom,mode
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- reg
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additionalProperties: false
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examples:
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- |
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#include <dt-bindings/clock/qcom,gcc-msm8960.h>
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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#include <dt-bindings/soc/qcom,gsbi.h>
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gsbi@12440000 {
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compatible = "qcom,gsbi-v1.0.0";
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reg = <0x12440000 0x100>;
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cell-index = <1>;
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clocks = <&gcc GSBI1_H_CLK>;
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clock-names = "iface";
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#address-cells = <1>;
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#size-cells = <1>;
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ranges;
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syscon-tcsr = <&tcsr>;
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qcom,mode = <GSBI_PROT_I2C_UART>;
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serial@12450000 {
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compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm";
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reg = <0x12450000 0x100>,
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<0x12400000 0x03>;
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interrupts = <0 193 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&gcc GSBI1_UART_CLK>, <&gcc GSBI1_H_CLK>;
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clock-names = "core", "iface";
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};
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i2c@12460000 {
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compatible = "qcom,i2c-qup-v1.1.1";
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reg = <0x12460000 0x1000>;
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pinctrl-0 = <&i2c1_pins>;
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pinctrl-1 = <&i2c1_pins_sleep>;
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pinctrl-names = "default", "sleep";
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interrupts = <0 194 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&gcc GSBI1_QUP_CLK>, <&gcc GSBI1_H_CLK>;
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clock-names = "core", "iface";
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#address-cells = <1>;
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#size-cells = <0>;
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status = "disabled"; /* UART chosen */
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};
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};
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