268 lines
8.2 KiB
YAML
268 lines
8.2 KiB
YAML
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# SPDX-License-Identifier: GPL-2.0-only
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/soc/qcom/qcom,rpmh-rsc.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: Qualcomm RPMH RSC
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maintainers:
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- Bjorn Andersson <bjorn.andersson@linaro.org>
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description: |
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Resource Power Manager Hardened (RPMH) is the mechanism for communicating
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with the hardened resource accelerators on Qualcomm SoCs. Requests to the
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resources can be written to the Trigger Command Set (TCS) registers and
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using a (addr, val) pair and triggered. Messages in the TCS are then sent in
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sequence over an internal bus.
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The hardware block (Direct Resource Voter or DRV) is a part of the h/w entity
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(Resource State Coordinator a.k.a RSC) that can handle multiple sleep and
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active/wake resource requests. Multiple such DRVs can exist in a SoC and can
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be written to from Linux. The structure of each DRV follows the same template
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with a few variations that are captured by the properties here.
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A TCS may be triggered from Linux or triggered by the F/W after all the CPUs
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have powered off to facilitate idle power saving. TCS could be classified as::
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ACTIVE - Triggered by Linux
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SLEEP - Triggered by F/W
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WAKE - Triggered by F/W
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CONTROL - Triggered by F/W
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See also:: <dt-bindings/soc/qcom,rpmh-rsc.h>
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The order in which they are described in the DT, should match the hardware
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configuration.
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Requests can be made for the state of a resource, when the subsystem is
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active or idle. When all subsystems like Modem, GPU, CPU are idle, the
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resource state will be an aggregate of the sleep votes from each of those
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subsystems. Clients may request a sleep value for their shared resources in
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addition to the active mode requests.
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Drivers that want to use the RSC to communicate with RPMH must specify their
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bindings as child nodes of the RSC controllers they wish to communicate with.
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properties:
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compatible:
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const: qcom,rpmh-rsc
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interrupts:
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minItems: 1
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maxItems: 4
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description:
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The interrupt that trips when a message complete/response is received for
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this DRV from the accelerators.
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Number of interrupts must match number of DRV blocks.
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label:
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description:
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Name for the RSC. The name would be used in trace logs.
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qcom,drv-id:
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$ref: /schemas/types.yaml#/definitions/uint32
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description:
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The ID of the DRV in the RSC block that will be used by this controller.
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qcom,tcs-config:
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$ref: /schemas/types.yaml#/definitions/uint32-matrix
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minItems: 4
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maxItems: 4
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items:
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items:
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- description: |
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TCS type::
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- ACTIVE_TCS
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- SLEEP_TCS
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- WAKE_TCS
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- CONTROL_TCS
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enum: [ 0, 1, 2, 3 ]
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- description: Number of TCS
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description: |
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The tuple defining the configuration of TCS. Must have two cells which
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describe each TCS type. The order of the TCS must match the hardware
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configuration.
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qcom,tcs-offset:
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$ref: /schemas/types.yaml#/definitions/uint32
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description:
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The offset of the TCS blocks.
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reg:
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minItems: 1
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maxItems: 4
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reg-names:
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minItems: 1
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items:
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- const: drv-0
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- const: drv-1
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- const: drv-2
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- const: drv-3
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power-domains:
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maxItems: 1
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bcm-voter:
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$ref: /schemas/interconnect/qcom,bcm-voter.yaml#
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clock-controller:
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$ref: /schemas/clock/qcom,rpmhcc.yaml#
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power-controller:
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$ref: /schemas/power/qcom,rpmpd.yaml#
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patternProperties:
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'^regulators(-[0-9])?$':
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$ref: /schemas/regulator/qcom,rpmh-regulator.yaml#
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unevaluatedProperties: false
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required:
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- compatible
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- interrupts
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- qcom,drv-id
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- qcom,tcs-config
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- qcom,tcs-offset
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- reg
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- reg-names
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additionalProperties: false
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examples:
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- |
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// For a TCS whose RSC base address is 0x179C0000 and is at a DRV id of
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// 2, the register offsets for DRV2 start at 0D00, the register
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// calculations are like this::
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// DRV0: 0x179C0000
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// DRV2: 0x179C0000 + 0x10000 = 0x179D0000
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// DRV2: 0x179C0000 + 0x10000 * 2 = 0x179E0000
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// TCS-OFFSET: 0xD00
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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#include <dt-bindings/soc/qcom,rpmh-rsc.h>
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rsc@179c0000 {
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compatible = "qcom,rpmh-rsc";
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reg = <0x179c0000 0x10000>,
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<0x179d0000 0x10000>,
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<0x179e0000 0x10000>;
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reg-names = "drv-0", "drv-1", "drv-2";
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interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
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label = "apps_rsc";
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qcom,tcs-offset = <0xd00>;
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qcom,drv-id = <2>;
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qcom,tcs-config = <ACTIVE_TCS 2>,
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<SLEEP_TCS 3>,
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<WAKE_TCS 3>,
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<CONTROL_TCS 1>;
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power-domains = <&CLUSTER_PD>;
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};
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- |
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// For a TCS whose RSC base address is 0xAF20000 and is at DRV id of 0, the
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// register offsets for DRV0 start at 01C00, the register calculations are
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// like this::
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// DRV0: 0xAF20000
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// TCS-OFFSET: 0x1C00
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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#include <dt-bindings/soc/qcom,rpmh-rsc.h>
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rsc@af20000 {
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compatible = "qcom,rpmh-rsc";
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reg = <0xaf20000 0x10000>;
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reg-names = "drv-0";
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interrupts = <GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>;
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label = "disp_rsc";
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qcom,tcs-offset = <0x1c00>;
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qcom,drv-id = <0>;
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qcom,tcs-config = <ACTIVE_TCS 0>,
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<SLEEP_TCS 1>,
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<WAKE_TCS 1>,
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<CONTROL_TCS 0>;
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};
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- |
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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#include <dt-bindings/soc/qcom,rpmh-rsc.h>
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#include <dt-bindings/power/qcom-rpmpd.h>
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rsc@18200000 {
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compatible = "qcom,rpmh-rsc";
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reg = <0x18200000 0x10000>,
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<0x18210000 0x10000>,
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<0x18220000 0x10000>;
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reg-names = "drv-0", "drv-1", "drv-2";
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interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
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label = "apps_rsc";
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qcom,tcs-offset = <0xd00>;
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qcom,drv-id = <2>;
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qcom,tcs-config = <ACTIVE_TCS 2>,
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<SLEEP_TCS 3>,
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<WAKE_TCS 3>,
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<CONTROL_TCS 0>;
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power-domains = <&CLUSTER_PD>;
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clock-controller {
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compatible = "qcom,sm8350-rpmh-clk";
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#clock-cells = <1>;
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clock-names = "xo";
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clocks = <&xo_board>;
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};
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power-controller {
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compatible = "qcom,sm8350-rpmhpd";
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#power-domain-cells = <1>;
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operating-points-v2 = <&rpmhpd_opp_table>;
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rpmhpd_opp_table: opp-table {
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compatible = "operating-points-v2";
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rpmhpd_opp_ret: opp1 {
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opp-level = <RPMH_REGULATOR_LEVEL_RETENTION>;
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};
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rpmhpd_opp_min_svs: opp2 {
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opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>;
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};
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rpmhpd_opp_low_svs: opp3 {
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opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
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};
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rpmhpd_opp_svs: opp4 {
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opp-level = <RPMH_REGULATOR_LEVEL_SVS>;
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};
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rpmhpd_opp_svs_l1: opp5 {
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opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
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};
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rpmhpd_opp_nom: opp6 {
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opp-level = <RPMH_REGULATOR_LEVEL_NOM>;
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};
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rpmhpd_opp_nom_l1: opp7 {
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opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>;
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};
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rpmhpd_opp_nom_l2: opp8 {
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opp-level = <RPMH_REGULATOR_LEVEL_NOM_L2>;
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};
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rpmhpd_opp_turbo: opp9 {
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opp-level = <RPMH_REGULATOR_LEVEL_TURBO>;
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};
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rpmhpd_opp_turbo_l1: opp10 {
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opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>;
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};
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};
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};
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bcm-voter {
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compatible = "qcom,bcm-voter";
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};
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};
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