176 lines
5.6 KiB
YAML
176 lines
5.6 KiB
YAML
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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/sound/mt8186-afe-pcm.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: Mediatek AFE PCM controller for mt8186
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maintainers:
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- Jiaxin Yu <jiaxin.yu@mediatek.com>
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properties:
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compatible:
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const: mediatek,mt8186-sound
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reg:
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maxItems: 1
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interrupts:
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maxItems: 1
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resets:
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maxItems: 1
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reset-names:
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const: audiosys
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mediatek,apmixedsys:
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$ref: "/schemas/types.yaml#/definitions/phandle"
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description: The phandle of the mediatek apmixedsys controller
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mediatek,infracfg:
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$ref: "/schemas/types.yaml#/definitions/phandle"
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description: The phandle of the mediatek infracfg controller
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mediatek,topckgen:
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$ref: "/schemas/types.yaml#/definitions/phandle"
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description: The phandle of the mediatek topckgen controller
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clocks:
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items:
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- description: audio infra sys clock
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- description: audio infra 26M clock
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- description: audio top mux
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- description: audio intbus mux
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- description: mainpll 136.5M clock
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- description: faud1 mux
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- description: apll1 clock
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- description: faud2 mux
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- description: apll2 clock
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- description: audio engen1 mux
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- description: apll1_d8 22.5792M clock
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- description: audio engen2 mux
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- description: apll2_d8 24.576M clock
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- description: i2s0 mclk mux
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- description: i2s1 mclk mux
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- description: i2s2 mclk mux
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- description: i2s4 mclk mux
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- description: tdm mclk mux
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- description: i2s0_mck divider
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- description: i2s1_mck divider
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- description: i2s2_mck divider
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- description: i2s4_mck divider
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- description: tdm_mck divider
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- description: audio hires mux
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- description: 26M clock
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clock-names:
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items:
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- const: aud_infra_clk
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- const: mtkaif_26m_clk
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- const: top_mux_audio
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- const: top_mux_audio_int
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- const: top_mainpll_d2_d4
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- const: top_mux_aud_1
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- const: top_apll1_ck
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- const: top_mux_aud_2
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- const: top_apll2_ck
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- const: top_mux_aud_eng1
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- const: top_apll1_d8
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- const: top_mux_aud_eng2
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- const: top_apll2_d8
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- const: top_i2s0_m_sel
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- const: top_i2s1_m_sel
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- const: top_i2s2_m_sel
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- const: top_i2s4_m_sel
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- const: top_tdm_m_sel
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- const: top_apll12_div0
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- const: top_apll12_div1
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- const: top_apll12_div2
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- const: top_apll12_div4
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- const: top_apll12_div_tdm
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- const: top_mux_audio_h
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- const: top_clk26m_clk
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required:
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- compatible
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- interrupts
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- resets
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- reset-names
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- mediatek,apmixedsys
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- mediatek,infracfg
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- mediatek,topckgen
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- clocks
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- clock-names
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additionalProperties: false
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examples:
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- |
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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#include <dt-bindings/interrupt-controller/irq.h>
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afe: mt8186-afe-pcm@11210000 {
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compatible = "mediatek,mt8186-sound";
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reg = <0x11210000 0x2000>;
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interrupts = <GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH>;
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resets = <&watchdog 17>; //MT8186_TOPRGU_AUDIO_SW_RST
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reset-names = "audiosys";
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mediatek,apmixedsys = <&apmixedsys>;
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mediatek,infracfg = <&infracfg>;
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mediatek,topckgen = <&topckgen>;
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clocks = <&infracfg_ao 44>, //CLK_INFRA_AO_AUDIO
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<&infracfg_ao 54>, //CLK_INFRA_AO_AUDIO_26M_BCLK
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<&topckgen 15>, //CLK_TOP_AUDIO
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<&topckgen 16>, //CLK_TOP_AUD_INTBUS
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<&topckgen 70>, //CLK_TOP_MAINPLL_D2_D4
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<&topckgen 17>, //CLK_TOP_AUD_1
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<&apmixedsys 12>, //CLK_APMIXED_APLL1
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<&topckgen 18>, //CLK_TOP_AUD_2
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<&apmixedsys 13>, //CLK_APMIXED_APLL2
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<&topckgen 19>, //CLK_TOP_AUD_ENGEN1
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<&topckgen 101>, //CLK_TOP_APLL1_D8
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<&topckgen 20>, //CLK_TOP_AUD_ENGEN2
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<&topckgen 104>, //CLK_TOP_APLL2_D8
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<&topckgen 63>, //CLK_TOP_APLL_I2S0_MCK_SEL
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<&topckgen 64>, //CLK_TOP_APLL_I2S1_MCK_SEL
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<&topckgen 65>, //CLK_TOP_APLL_I2S2_MCK_SEL
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<&topckgen 66>, //CLK_TOP_APLL_I2S4_MCK_SEL
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<&topckgen 67>, //CLK_TOP_APLL_TDMOUT_MCK_SEL
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<&topckgen 131>, //CLK_TOP_APLL12_CK_DIV0
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<&topckgen 132>, //CLK_TOP_APLL12_CK_DIV1
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<&topckgen 133>, //CLK_TOP_APLL12_CK_DIV2
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<&topckgen 134>, //CLK_TOP_APLL12_CK_DIV4
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<&topckgen 135>, //CLK_TOP_APLL12_CK_DIV_TDMOUT_M
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<&topckgen 44>, //CLK_TOP_AUDIO_H
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<&clk26m>;
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clock-names = "aud_infra_clk",
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"mtkaif_26m_clk",
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"top_mux_audio",
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"top_mux_audio_int",
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"top_mainpll_d2_d4",
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"top_mux_aud_1",
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"top_apll1_ck",
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"top_mux_aud_2",
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"top_apll2_ck",
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"top_mux_aud_eng1",
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"top_apll1_d8",
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"top_mux_aud_eng2",
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"top_apll2_d8",
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"top_i2s0_m_sel",
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"top_i2s1_m_sel",
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"top_i2s2_m_sel",
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"top_i2s4_m_sel",
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"top_tdm_m_sel",
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"top_apll12_div0",
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"top_apll12_div1",
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"top_apll12_div2",
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"top_apll12_div4",
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"top_apll12_div_tdm",
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"top_mux_audio_h",
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"top_clk26m_clk";
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};
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...
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