110 lines
3.3 KiB
YAML
110 lines
3.3 KiB
YAML
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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
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%YAML 1.2
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---
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$id: "http://devicetree.org/schemas/timer/nvidia,tegra186-timer.yaml#"
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$schema: "http://devicetree.org/meta-schemas/core.yaml#"
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title: NVIDIA Tegra186 timer
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maintainers:
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- Thierry Reding <treding@nvidia.com>
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description: >
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The Tegra timer provides 29-bit timer counters and a 32-bit timestamp
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counter. Each NV timer selects its timing reference signal from the 1 MHz
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reference generated by USEC, TSC or either clk_m or OSC. Each TMR can be
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programmed to generate one-shot, periodic, or watchdog interrupts.
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properties:
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compatible:
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oneOf:
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- const: nvidia,tegra186-timer
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description: >
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The Tegra186 timer provides ten 29-bit timer counters.
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- const: nvidia,tegra234-timer
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description: >
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The Tegra234 timer provides sixteen 29-bit timer counters.
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reg:
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maxItems: 1
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interrupts: true
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allOf:
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- if:
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properties:
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compatible:
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contains:
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const: nvidia,tegra186-timer
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then:
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properties:
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interrupts:
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maxItems: 10
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description: >
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One per each timer channels 0 through 9.
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- if:
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properties:
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compatible:
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contains:
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const: nvidia,tegra234-timer
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then:
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properties:
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interrupts:
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maxItems: 16
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description: >
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One per each timer channels 0 through 15.
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required:
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- compatible
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- reg
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- interrupts
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additionalProperties: false
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examples:
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- |
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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#include <dt-bindings/interrupt-controller/irq.h>
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timer@3010000 {
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compatible = "nvidia,tegra186-timer";
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reg = <0x03010000 0x000e0000>;
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interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
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};
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- |
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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#include <dt-bindings/interrupt-controller/irq.h>
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timer@2080000 {
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compatible = "nvidia,tegra234-timer";
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reg = <0x02080000 0x00121000>;
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interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
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};
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