205 lines
8.0 KiB
YAML
205 lines
8.0 KiB
YAML
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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/timer/renesas,cmt.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: Renesas Compare Match Timer (CMT)
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maintainers:
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- Geert Uytterhoeven <geert+renesas@glider.be>
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- Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
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description:
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The CMT is a multi-channel 16/32/48-bit timer/counter with configurable clock
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inputs and programmable compare match.
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Channels share hardware resources but their counter and compare match values
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are independent. A particular CMT instance can implement only a subset of the
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channels supported by the CMT model. Channel indices represent the hardware
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position of the channel in the CMT and don't match the channel numbers in the
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datasheets.
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properties:
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compatible:
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oneOf:
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- items:
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- enum:
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- renesas,r8a7740-cmt0 # 32-bit CMT0 on R-Mobile A1
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- renesas,r8a7740-cmt1 # 48-bit CMT1 on R-Mobile A1
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- renesas,r8a7740-cmt2 # 32-bit CMT2 on R-Mobile A1
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- renesas,r8a7740-cmt3 # 32-bit CMT3 on R-Mobile A1
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- renesas,r8a7740-cmt4 # 32-bit CMT4 on R-Mobile A1
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- renesas,sh73a0-cmt0 # 32-bit CMT0 on SH-Mobile AG5
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- renesas,sh73a0-cmt1 # 48-bit CMT1 on SH-Mobile AG5
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- renesas,sh73a0-cmt2 # 32-bit CMT2 on SH-Mobile AG5
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- renesas,sh73a0-cmt3 # 32-bit CMT3 on SH-Mobile AG5
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- renesas,sh73a0-cmt4 # 32-bit CMT4 on SH-Mobile AG5
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- items:
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- enum:
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- renesas,r8a73a4-cmt0 # 32-bit CMT0 on R-Mobile APE6
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- renesas,r8a7742-cmt0 # 32-bit CMT0 on RZ/G1H
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- renesas,r8a7743-cmt0 # 32-bit CMT0 on RZ/G1M
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- renesas,r8a7744-cmt0 # 32-bit CMT0 on RZ/G1N
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- renesas,r8a7745-cmt0 # 32-bit CMT0 on RZ/G1E
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- renesas,r8a77470-cmt0 # 32-bit CMT0 on RZ/G1C
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- renesas,r8a7790-cmt0 # 32-bit CMT0 on R-Car H2
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- renesas,r8a7791-cmt0 # 32-bit CMT0 on R-Car M2-W
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- renesas,r8a7792-cmt0 # 32-bit CMT0 on R-Car V2H
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- renesas,r8a7793-cmt0 # 32-bit CMT0 on R-Car M2-N
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- renesas,r8a7794-cmt0 # 32-bit CMT0 on R-Car E2
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- const: renesas,rcar-gen2-cmt0 # 32-bit CMT0 on R-Mobile APE6, R-Car Gen2 and RZ/G1
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- items:
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- enum:
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- renesas,r8a73a4-cmt1 # 48-bit CMT1 on R-Mobile APE6
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- renesas,r8a7742-cmt1 # 48-bit CMT1 on RZ/G1H
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- renesas,r8a7743-cmt1 # 48-bit CMT1 on RZ/G1M
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- renesas,r8a7744-cmt1 # 48-bit CMT1 on RZ/G1N
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- renesas,r8a7745-cmt1 # 48-bit CMT1 on RZ/G1E
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- renesas,r8a77470-cmt1 # 48-bit CMT1 on RZ/G1C
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- renesas,r8a7790-cmt1 # 48-bit CMT1 on R-Car H2
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- renesas,r8a7791-cmt1 # 48-bit CMT1 on R-Car M2-W
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- renesas,r8a7792-cmt1 # 48-bit CMT1 on R-Car V2H
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- renesas,r8a7793-cmt1 # 48-bit CMT1 on R-Car M2-N
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- renesas,r8a7794-cmt1 # 48-bit CMT1 on R-Car E2
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- const: renesas,rcar-gen2-cmt1 # 48-bit CMT1 on R-Mobile APE6, R-Car Gen2 and RZ/G1
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- items:
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- enum:
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- renesas,r8a774a1-cmt0 # 32-bit CMT0 on RZ/G2M
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- renesas,r8a774b1-cmt0 # 32-bit CMT0 on RZ/G2N
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- renesas,r8a774c0-cmt0 # 32-bit CMT0 on RZ/G2E
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- renesas,r8a774e1-cmt0 # 32-bit CMT0 on RZ/G2H
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- renesas,r8a7795-cmt0 # 32-bit CMT0 on R-Car H3
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- renesas,r8a7796-cmt0 # 32-bit CMT0 on R-Car M3-W
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- renesas,r8a77961-cmt0 # 32-bit CMT0 on R-Car M3-W+
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- renesas,r8a77965-cmt0 # 32-bit CMT0 on R-Car M3-N
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- renesas,r8a77970-cmt0 # 32-bit CMT0 on R-Car V3M
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- renesas,r8a77980-cmt0 # 32-bit CMT0 on R-Car V3H
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- renesas,r8a77990-cmt0 # 32-bit CMT0 on R-Car E3
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- renesas,r8a77995-cmt0 # 32-bit CMT0 on R-Car D3
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- const: renesas,rcar-gen3-cmt0 # 32-bit CMT0 on R-Car Gen3 and RZ/G2
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- items:
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- enum:
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- renesas,r8a774a1-cmt1 # 48-bit CMT on RZ/G2M
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- renesas,r8a774b1-cmt1 # 48-bit CMT on RZ/G2N
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- renesas,r8a774c0-cmt1 # 48-bit CMT on RZ/G2E
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- renesas,r8a774e1-cmt1 # 48-bit CMT on RZ/G2H
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- renesas,r8a7795-cmt1 # 48-bit CMT on R-Car H3
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- renesas,r8a7796-cmt1 # 48-bit CMT on R-Car M3-W
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- renesas,r8a77961-cmt1 # 48-bit CMT on R-Car M3-W+
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- renesas,r8a77965-cmt1 # 48-bit CMT on R-Car M3-N
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- renesas,r8a77970-cmt1 # 48-bit CMT on R-Car V3M
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- renesas,r8a77980-cmt1 # 48-bit CMT on R-Car V3H
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- renesas,r8a77990-cmt1 # 48-bit CMT on R-Car E3
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- renesas,r8a77995-cmt1 # 48-bit CMT on R-Car D3
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- const: renesas,rcar-gen3-cmt1 # 48-bit CMT on R-Car Gen3 and RZ/G2
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- items:
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- enum:
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- renesas,r8a779a0-cmt0 # 32-bit CMT0 on R-Car V3U
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- renesas,r8a779f0-cmt0 # 32-bit CMT0 on R-Car S4-8
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- renesas,r8a779g0-cmt0 # 32-bit CMT0 on R-Car V4H
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- const: renesas,rcar-gen4-cmt0 # 32-bit CMT0 on R-Car Gen4
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- items:
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- enum:
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- renesas,r8a779a0-cmt1 # 48-bit CMT on R-Car V3U
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- renesas,r8a779f0-cmt1 # 48-bit CMT on R-Car S4-8
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- renesas,r8a779g0-cmt1 # 48-bit CMT on R-Car V4H
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- const: renesas,rcar-gen4-cmt1 # 48-bit CMT on R-Car Gen4
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reg:
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maxItems: 1
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interrupts:
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minItems: 1
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maxItems: 8
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clocks:
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maxItems: 1
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clock-names:
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const: fck
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power-domains:
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maxItems: 1
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resets:
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maxItems: 1
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required:
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- compatible
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- reg
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- interrupts
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- clocks
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- clock-names
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- power-domains
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allOf:
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- if:
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properties:
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compatible:
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contains:
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enum:
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- renesas,rcar-gen2-cmt0
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- renesas,rcar-gen3-cmt0
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- renesas,rcar-gen4-cmt0
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then:
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properties:
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interrupts:
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minItems: 2
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maxItems: 2
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- if:
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properties:
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compatible:
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contains:
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enum:
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- renesas,rcar-gen2-cmt1
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- renesas,rcar-gen3-cmt1
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- renesas,rcar-gen4-cmt1
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then:
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properties:
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interrupts:
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minItems: 8
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maxItems: 8
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additionalProperties: false
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examples:
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- |
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#include <dt-bindings/clock/r8a7790-cpg-mssr.h>
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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#include <dt-bindings/power/r8a7790-sysc.h>
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cmt0: timer@ffca0000 {
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compatible = "renesas,r8a7790-cmt0", "renesas,rcar-gen2-cmt0";
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reg = <0xffca0000 0x1004>;
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interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&cpg CPG_MOD 124>;
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clock-names = "fck";
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power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
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resets = <&cpg 124>;
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};
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cmt1: timer@e6130000 {
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compatible = "renesas,r8a7790-cmt1", "renesas,rcar-gen2-cmt1";
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reg = <0xe6130000 0x1004>;
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interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&cpg CPG_MOD 329>;
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clock-names = "fck";
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power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
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resets = <&cpg 329>;
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};
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