839 lines
21 KiB
Plaintext
839 lines
21 KiB
Plaintext
|
// SPDX-License-Identifier: GPL-2.0+ OR MIT
|
||
|
|
/*
|
||
|
|
* Apple T8103 "M1" SoC
|
||
|
|
*
|
||
|
|
* Other names: H13G, "Tonga"
|
||
|
|
*
|
||
|
|
* Copyright The Asahi Linux Contributors
|
||
|
|
*/
|
||
|
|
|
||
|
|
#include <dt-bindings/gpio/gpio.h>
|
||
|
|
#include <dt-bindings/interrupt-controller/apple-aic.h>
|
||
|
|
#include <dt-bindings/interrupt-controller/irq.h>
|
||
|
|
#include <dt-bindings/pinctrl/apple.h>
|
||
|
|
|
||
|
|
/ {
|
||
|
|
compatible = "apple,t8103", "apple,arm-platform";
|
||
|
|
|
||
|
|
#address-cells = <2>;
|
||
|
|
#size-cells = <2>;
|
||
|
|
|
||
|
|
cpus {
|
||
|
|
#address-cells = <2>;
|
||
|
|
#size-cells = <0>;
|
||
|
|
|
||
|
|
cpu-map {
|
||
|
|
cluster0 {
|
||
|
|
core0 {
|
||
|
|
cpu = <&cpu_e0>;
|
||
|
|
};
|
||
|
|
core1 {
|
||
|
|
cpu = <&cpu_e1>;
|
||
|
|
};
|
||
|
|
core2 {
|
||
|
|
cpu = <&cpu_e2>;
|
||
|
|
};
|
||
|
|
core3 {
|
||
|
|
cpu = <&cpu_e3>;
|
||
|
|
};
|
||
|
|
};
|
||
|
|
|
||
|
|
cluster1 {
|
||
|
|
core0 {
|
||
|
|
cpu = <&cpu_p0>;
|
||
|
|
};
|
||
|
|
core1 {
|
||
|
|
cpu = <&cpu_p1>;
|
||
|
|
};
|
||
|
|
core2 {
|
||
|
|
cpu = <&cpu_p2>;
|
||
|
|
};
|
||
|
|
core3 {
|
||
|
|
cpu = <&cpu_p3>;
|
||
|
|
};
|
||
|
|
};
|
||
|
|
};
|
||
|
|
|
||
|
|
cpu_e0: cpu@0 {
|
||
|
|
compatible = "apple,icestorm";
|
||
|
|
device_type = "cpu";
|
||
|
|
reg = <0x0 0x0>;
|
||
|
|
enable-method = "spin-table";
|
||
|
|
cpu-release-addr = <0 0>; /* To be filled by loader */
|
||
|
|
operating-points-v2 = <&ecluster_opp>;
|
||
|
|
capacity-dmips-mhz = <714>;
|
||
|
|
performance-domains = <&cpufreq_e>;
|
||
|
|
next-level-cache = <&l2_cache_0>;
|
||
|
|
i-cache-size = <0x20000>;
|
||
|
|
d-cache-size = <0x10000>;
|
||
|
|
};
|
||
|
|
|
||
|
|
cpu_e1: cpu@1 {
|
||
|
|
compatible = "apple,icestorm";
|
||
|
|
device_type = "cpu";
|
||
|
|
reg = <0x0 0x1>;
|
||
|
|
enable-method = "spin-table";
|
||
|
|
cpu-release-addr = <0 0>; /* To be filled by loader */
|
||
|
|
operating-points-v2 = <&ecluster_opp>;
|
||
|
|
capacity-dmips-mhz = <714>;
|
||
|
|
performance-domains = <&cpufreq_e>;
|
||
|
|
next-level-cache = <&l2_cache_0>;
|
||
|
|
i-cache-size = <0x20000>;
|
||
|
|
d-cache-size = <0x10000>;
|
||
|
|
};
|
||
|
|
|
||
|
|
cpu_e2: cpu@2 {
|
||
|
|
compatible = "apple,icestorm";
|
||
|
|
device_type = "cpu";
|
||
|
|
reg = <0x0 0x2>;
|
||
|
|
enable-method = "spin-table";
|
||
|
|
cpu-release-addr = <0 0>; /* To be filled by loader */
|
||
|
|
operating-points-v2 = <&ecluster_opp>;
|
||
|
|
capacity-dmips-mhz = <714>;
|
||
|
|
performance-domains = <&cpufreq_e>;
|
||
|
|
next-level-cache = <&l2_cache_0>;
|
||
|
|
i-cache-size = <0x20000>;
|
||
|
|
d-cache-size = <0x10000>;
|
||
|
|
};
|
||
|
|
|
||
|
|
cpu_e3: cpu@3 {
|
||
|
|
compatible = "apple,icestorm";
|
||
|
|
device_type = "cpu";
|
||
|
|
reg = <0x0 0x3>;
|
||
|
|
enable-method = "spin-table";
|
||
|
|
cpu-release-addr = <0 0>; /* To be filled by loader */
|
||
|
|
operating-points-v2 = <&ecluster_opp>;
|
||
|
|
capacity-dmips-mhz = <714>;
|
||
|
|
performance-domains = <&cpufreq_e>;
|
||
|
|
next-level-cache = <&l2_cache_0>;
|
||
|
|
i-cache-size = <0x20000>;
|
||
|
|
d-cache-size = <0x10000>;
|
||
|
|
};
|
||
|
|
|
||
|
|
cpu_p0: cpu@10100 {
|
||
|
|
compatible = "apple,firestorm";
|
||
|
|
device_type = "cpu";
|
||
|
|
reg = <0x0 0x10100>;
|
||
|
|
enable-method = "spin-table";
|
||
|
|
cpu-release-addr = <0 0>; /* To be filled by loader */
|
||
|
|
operating-points-v2 = <&pcluster_opp>;
|
||
|
|
capacity-dmips-mhz = <1024>;
|
||
|
|
performance-domains = <&cpufreq_p>;
|
||
|
|
next-level-cache = <&l2_cache_1>;
|
||
|
|
i-cache-size = <0x30000>;
|
||
|
|
d-cache-size = <0x20000>;
|
||
|
|
};
|
||
|
|
|
||
|
|
cpu_p1: cpu@10101 {
|
||
|
|
compatible = "apple,firestorm";
|
||
|
|
device_type = "cpu";
|
||
|
|
reg = <0x0 0x10101>;
|
||
|
|
enable-method = "spin-table";
|
||
|
|
cpu-release-addr = <0 0>; /* To be filled by loader */
|
||
|
|
operating-points-v2 = <&pcluster_opp>;
|
||
|
|
capacity-dmips-mhz = <1024>;
|
||
|
|
performance-domains = <&cpufreq_p>;
|
||
|
|
next-level-cache = <&l2_cache_1>;
|
||
|
|
i-cache-size = <0x30000>;
|
||
|
|
d-cache-size = <0x20000>;
|
||
|
|
};
|
||
|
|
|
||
|
|
cpu_p2: cpu@10102 {
|
||
|
|
compatible = "apple,firestorm";
|
||
|
|
device_type = "cpu";
|
||
|
|
reg = <0x0 0x10102>;
|
||
|
|
enable-method = "spin-table";
|
||
|
|
cpu-release-addr = <0 0>; /* To be filled by loader */
|
||
|
|
operating-points-v2 = <&pcluster_opp>;
|
||
|
|
capacity-dmips-mhz = <1024>;
|
||
|
|
performance-domains = <&cpufreq_p>;
|
||
|
|
next-level-cache = <&l2_cache_1>;
|
||
|
|
i-cache-size = <0x30000>;
|
||
|
|
d-cache-size = <0x20000>;
|
||
|
|
};
|
||
|
|
|
||
|
|
cpu_p3: cpu@10103 {
|
||
|
|
compatible = "apple,firestorm";
|
||
|
|
device_type = "cpu";
|
||
|
|
reg = <0x0 0x10103>;
|
||
|
|
enable-method = "spin-table";
|
||
|
|
cpu-release-addr = <0 0>; /* To be filled by loader */
|
||
|
|
operating-points-v2 = <&pcluster_opp>;
|
||
|
|
capacity-dmips-mhz = <1024>;
|
||
|
|
performance-domains = <&cpufreq_p>;
|
||
|
|
next-level-cache = <&l2_cache_1>;
|
||
|
|
i-cache-size = <0x30000>;
|
||
|
|
d-cache-size = <0x20000>;
|
||
|
|
};
|
||
|
|
|
||
|
|
l2_cache_0: l2-cache-0 {
|
||
|
|
compatible = "cache";
|
||
|
|
cache-level = <2>;
|
||
|
|
cache-unified;
|
||
|
|
cache-size = <0x400000>;
|
||
|
|
};
|
||
|
|
|
||
|
|
l2_cache_1: l2-cache-1 {
|
||
|
|
compatible = "cache";
|
||
|
|
cache-level = <2>;
|
||
|
|
cache-unified;
|
||
|
|
cache-size = <0xc00000>;
|
||
|
|
};
|
||
|
|
};
|
||
|
|
|
||
|
|
ecluster_opp: opp-table-0 {
|
||
|
|
compatible = "operating-points-v2";
|
||
|
|
|
||
|
|
opp01 {
|
||
|
|
opp-hz = /bits/ 64 <600000000>;
|
||
|
|
opp-level = <1>;
|
||
|
|
clock-latency-ns = <7500>;
|
||
|
|
};
|
||
|
|
opp02 {
|
||
|
|
opp-hz = /bits/ 64 <972000000>;
|
||
|
|
opp-level = <2>;
|
||
|
|
clock-latency-ns = <22000>;
|
||
|
|
};
|
||
|
|
opp03 {
|
||
|
|
opp-hz = /bits/ 64 <1332000000>;
|
||
|
|
opp-level = <3>;
|
||
|
|
clock-latency-ns = <27000>;
|
||
|
|
};
|
||
|
|
opp04 {
|
||
|
|
opp-hz = /bits/ 64 <1704000000>;
|
||
|
|
opp-level = <4>;
|
||
|
|
clock-latency-ns = <33000>;
|
||
|
|
};
|
||
|
|
opp05 {
|
||
|
|
opp-hz = /bits/ 64 <2064000000>;
|
||
|
|
opp-level = <5>;
|
||
|
|
clock-latency-ns = <50000>;
|
||
|
|
};
|
||
|
|
};
|
||
|
|
|
||
|
|
pcluster_opp: opp-table-1 {
|
||
|
|
compatible = "operating-points-v2";
|
||
|
|
|
||
|
|
opp01 {
|
||
|
|
opp-hz = /bits/ 64 <600000000>;
|
||
|
|
opp-level = <1>;
|
||
|
|
clock-latency-ns = <8000>;
|
||
|
|
};
|
||
|
|
opp02 {
|
||
|
|
opp-hz = /bits/ 64 <828000000>;
|
||
|
|
opp-level = <2>;
|
||
|
|
clock-latency-ns = <19000>;
|
||
|
|
};
|
||
|
|
opp03 {
|
||
|
|
opp-hz = /bits/ 64 <1056000000>;
|
||
|
|
opp-level = <3>;
|
||
|
|
clock-latency-ns = <21000>;
|
||
|
|
};
|
||
|
|
opp04 {
|
||
|
|
opp-hz = /bits/ 64 <1284000000>;
|
||
|
|
opp-level = <4>;
|
||
|
|
clock-latency-ns = <23000>;
|
||
|
|
};
|
||
|
|
opp05 {
|
||
|
|
opp-hz = /bits/ 64 <1500000000>;
|
||
|
|
opp-level = <5>;
|
||
|
|
clock-latency-ns = <24000>;
|
||
|
|
};
|
||
|
|
opp06 {
|
||
|
|
opp-hz = /bits/ 64 <1728000000>;
|
||
|
|
opp-level = <6>;
|
||
|
|
clock-latency-ns = <29000>;
|
||
|
|
};
|
||
|
|
opp07 {
|
||
|
|
opp-hz = /bits/ 64 <1956000000>;
|
||
|
|
opp-level = <7>;
|
||
|
|
clock-latency-ns = <31000>;
|
||
|
|
};
|
||
|
|
opp08 {
|
||
|
|
opp-hz = /bits/ 64 <2184000000>;
|
||
|
|
opp-level = <8>;
|
||
|
|
clock-latency-ns = <34000>;
|
||
|
|
};
|
||
|
|
opp09 {
|
||
|
|
opp-hz = /bits/ 64 <2388000000>;
|
||
|
|
opp-level = <9>;
|
||
|
|
clock-latency-ns = <36000>;
|
||
|
|
};
|
||
|
|
opp10 {
|
||
|
|
opp-hz = /bits/ 64 <2592000000>;
|
||
|
|
opp-level = <10>;
|
||
|
|
clock-latency-ns = <51000>;
|
||
|
|
};
|
||
|
|
opp11 {
|
||
|
|
opp-hz = /bits/ 64 <2772000000>;
|
||
|
|
opp-level = <11>;
|
||
|
|
clock-latency-ns = <54000>;
|
||
|
|
};
|
||
|
|
opp12 {
|
||
|
|
opp-hz = /bits/ 64 <2988000000>;
|
||
|
|
opp-level = <12>;
|
||
|
|
clock-latency-ns = <55000>;
|
||
|
|
};
|
||
|
|
#if 0
|
||
|
|
/* Not available until CPU deep sleep is implemented */
|
||
|
|
opp13 {
|
||
|
|
opp-hz = /bits/ 64 <3096000000>;
|
||
|
|
opp-level = <13>;
|
||
|
|
clock-latency-ns = <55000>;
|
||
|
|
turbo-mode;
|
||
|
|
};
|
||
|
|
opp14 {
|
||
|
|
opp-hz = /bits/ 64 <3144000000>;
|
||
|
|
opp-level = <14>;
|
||
|
|
clock-latency-ns = <56000>;
|
||
|
|
turbo-mode;
|
||
|
|
};
|
||
|
|
opp15 {
|
||
|
|
opp-hz = /bits/ 64 <3204000000>;
|
||
|
|
opp-level = <15>;
|
||
|
|
clock-latency-ns = <56000>;
|
||
|
|
turbo-mode;
|
||
|
|
};
|
||
|
|
#endif
|
||
|
|
};
|
||
|
|
|
||
|
|
timer {
|
||
|
|
compatible = "arm,armv8-timer";
|
||
|
|
interrupt-parent = <&aic>;
|
||
|
|
interrupt-names = "phys", "virt", "hyp-phys", "hyp-virt";
|
||
|
|
interrupts = <AIC_FIQ AIC_TMR_GUEST_PHYS IRQ_TYPE_LEVEL_HIGH>,
|
||
|
|
<AIC_FIQ AIC_TMR_GUEST_VIRT IRQ_TYPE_LEVEL_HIGH>,
|
||
|
|
<AIC_FIQ AIC_TMR_HV_PHYS IRQ_TYPE_LEVEL_HIGH>,
|
||
|
|
<AIC_FIQ AIC_TMR_HV_VIRT IRQ_TYPE_LEVEL_HIGH>;
|
||
|
|
};
|
||
|
|
|
||
|
|
pmu-e {
|
||
|
|
compatible = "apple,icestorm-pmu";
|
||
|
|
interrupt-parent = <&aic>;
|
||
|
|
interrupts = <AIC_FIQ AIC_CPU_PMU_E IRQ_TYPE_LEVEL_HIGH>;
|
||
|
|
};
|
||
|
|
|
||
|
|
pmu-p {
|
||
|
|
compatible = "apple,firestorm-pmu";
|
||
|
|
interrupt-parent = <&aic>;
|
||
|
|
interrupts = <AIC_FIQ AIC_CPU_PMU_P IRQ_TYPE_LEVEL_HIGH>;
|
||
|
|
};
|
||
|
|
|
||
|
|
clkref: clock-ref {
|
||
|
|
compatible = "fixed-clock";
|
||
|
|
#clock-cells = <0>;
|
||
|
|
clock-frequency = <24000000>;
|
||
|
|
clock-output-names = "clkref";
|
||
|
|
};
|
||
|
|
|
||
|
|
/*
|
||
|
|
* This is a fabulated representation of the input clock
|
||
|
|
* to NCO since we don't know the true clock tree.
|
||
|
|
*/
|
||
|
|
nco_clkref: clock-ref-nco {
|
||
|
|
compatible = "fixed-clock";
|
||
|
|
#clock-cells = <0>;
|
||
|
|
clock-output-names = "nco_ref";
|
||
|
|
};
|
||
|
|
|
||
|
|
soc {
|
||
|
|
compatible = "simple-bus";
|
||
|
|
#address-cells = <2>;
|
||
|
|
#size-cells = <2>;
|
||
|
|
|
||
|
|
ranges;
|
||
|
|
nonposted-mmio;
|
||
|
|
|
||
|
|
cpufreq_e: performance-controller@210e20000 {
|
||
|
|
compatible = "apple,t8103-cluster-cpufreq", "apple,cluster-cpufreq";
|
||
|
|
reg = <0x2 0x10e20000 0 0x1000>;
|
||
|
|
#performance-domain-cells = <0>;
|
||
|
|
};
|
||
|
|
|
||
|
|
cpufreq_p: performance-controller@211e20000 {
|
||
|
|
compatible = "apple,t8103-cluster-cpufreq", "apple,cluster-cpufreq";
|
||
|
|
reg = <0x2 0x11e20000 0 0x1000>;
|
||
|
|
#performance-domain-cells = <0>;
|
||
|
|
};
|
||
|
|
|
||
|
|
sio_dart: iommu@235004000 {
|
||
|
|
compatible = "apple,t8103-dart";
|
||
|
|
reg = <0x2 0x35004000 0x0 0x4000>;
|
||
|
|
interrupt-parent = <&aic>;
|
||
|
|
interrupts = <AIC_IRQ 635 IRQ_TYPE_LEVEL_HIGH>;
|
||
|
|
#iommu-cells = <1>;
|
||
|
|
power-domains = <&ps_sio_cpu>;
|
||
|
|
};
|
||
|
|
|
||
|
|
i2c0: i2c@235010000 {
|
||
|
|
compatible = "apple,t8103-i2c", "apple,i2c";
|
||
|
|
reg = <0x2 0x35010000 0x0 0x4000>;
|
||
|
|
clocks = <&clkref>;
|
||
|
|
interrupt-parent = <&aic>;
|
||
|
|
interrupts = <AIC_IRQ 627 IRQ_TYPE_LEVEL_HIGH>;
|
||
|
|
pinctrl-0 = <&i2c0_pins>;
|
||
|
|
pinctrl-names = "default";
|
||
|
|
#address-cells = <0x1>;
|
||
|
|
#size-cells = <0x0>;
|
||
|
|
power-domains = <&ps_i2c0>;
|
||
|
|
};
|
||
|
|
|
||
|
|
i2c1: i2c@235014000 {
|
||
|
|
compatible = "apple,t8103-i2c", "apple,i2c";
|
||
|
|
reg = <0x2 0x35014000 0x0 0x4000>;
|
||
|
|
clocks = <&clkref>;
|
||
|
|
interrupt-parent = <&aic>;
|
||
|
|
interrupts = <AIC_IRQ 628 IRQ_TYPE_LEVEL_HIGH>;
|
||
|
|
pinctrl-0 = <&i2c1_pins>;
|
||
|
|
pinctrl-names = "default";
|
||
|
|
#address-cells = <0x1>;
|
||
|
|
#size-cells = <0x0>;
|
||
|
|
power-domains = <&ps_i2c1>;
|
||
|
|
};
|
||
|
|
|
||
|
|
i2c2: i2c@235018000 {
|
||
|
|
compatible = "apple,t8103-i2c", "apple,i2c";
|
||
|
|
reg = <0x2 0x35018000 0x0 0x4000>;
|
||
|
|
clocks = <&clkref>;
|
||
|
|
interrupt-parent = <&aic>;
|
||
|
|
interrupts = <AIC_IRQ 629 IRQ_TYPE_LEVEL_HIGH>;
|
||
|
|
pinctrl-0 = <&i2c2_pins>;
|
||
|
|
pinctrl-names = "default";
|
||
|
|
#address-cells = <0x1>;
|
||
|
|
#size-cells = <0x0>;
|
||
|
|
status = "disabled"; /* not used in all devices */
|
||
|
|
power-domains = <&ps_i2c2>;
|
||
|
|
};
|
||
|
|
|
||
|
|
i2c3: i2c@23501c000 {
|
||
|
|
compatible = "apple,t8103-i2c", "apple,i2c";
|
||
|
|
reg = <0x2 0x3501c000 0x0 0x4000>;
|
||
|
|
clocks = <&clkref>;
|
||
|
|
interrupt-parent = <&aic>;
|
||
|
|
interrupts = <AIC_IRQ 630 IRQ_TYPE_LEVEL_HIGH>;
|
||
|
|
pinctrl-0 = <&i2c3_pins>;
|
||
|
|
pinctrl-names = "default";
|
||
|
|
#address-cells = <0x1>;
|
||
|
|
#size-cells = <0x0>;
|
||
|
|
power-domains = <&ps_i2c3>;
|
||
|
|
};
|
||
|
|
|
||
|
|
i2c4: i2c@235020000 {
|
||
|
|
compatible = "apple,t8103-i2c", "apple,i2c";
|
||
|
|
reg = <0x2 0x35020000 0x0 0x4000>;
|
||
|
|
clocks = <&clkref>;
|
||
|
|
interrupt-parent = <&aic>;
|
||
|
|
interrupts = <AIC_IRQ 631 IRQ_TYPE_LEVEL_HIGH>;
|
||
|
|
pinctrl-0 = <&i2c4_pins>;
|
||
|
|
pinctrl-names = "default";
|
||
|
|
#address-cells = <0x1>;
|
||
|
|
#size-cells = <0x0>;
|
||
|
|
power-domains = <&ps_i2c4>;
|
||
|
|
status = "disabled"; /* only used in J293 */
|
||
|
|
};
|
||
|
|
|
||
|
|
serial0: serial@235200000 {
|
||
|
|
compatible = "apple,s5l-uart";
|
||
|
|
reg = <0x2 0x35200000 0x0 0x1000>;
|
||
|
|
reg-io-width = <4>;
|
||
|
|
interrupt-parent = <&aic>;
|
||
|
|
interrupts = <AIC_IRQ 605 IRQ_TYPE_LEVEL_HIGH>;
|
||
|
|
/*
|
||
|
|
* TODO: figure out the clocking properly, there may
|
||
|
|
* be a third selectable clock.
|
||
|
|
*/
|
||
|
|
clocks = <&clkref>, <&clkref>;
|
||
|
|
clock-names = "uart", "clk_uart_baud0";
|
||
|
|
power-domains = <&ps_uart0>;
|
||
|
|
status = "disabled";
|
||
|
|
};
|
||
|
|
|
||
|
|
serial2: serial@235208000 {
|
||
|
|
compatible = "apple,s5l-uart";
|
||
|
|
reg = <0x2 0x35208000 0x0 0x1000>;
|
||
|
|
reg-io-width = <4>;
|
||
|
|
interrupt-parent = <&aic>;
|
||
|
|
interrupts = <AIC_IRQ 607 IRQ_TYPE_LEVEL_HIGH>;
|
||
|
|
clocks = <&clkref>, <&clkref>;
|
||
|
|
clock-names = "uart", "clk_uart_baud0";
|
||
|
|
power-domains = <&ps_uart2>;
|
||
|
|
status = "disabled";
|
||
|
|
};
|
||
|
|
|
||
|
|
admac: dma-controller@238200000 {
|
||
|
|
compatible = "apple,t8103-admac", "apple,admac";
|
||
|
|
reg = <0x2 0x38200000 0x0 0x34000>;
|
||
|
|
dma-channels = <24>;
|
||
|
|
interrupts-extended = <0>,
|
||
|
|
<&aic AIC_IRQ 626 IRQ_TYPE_LEVEL_HIGH>,
|
||
|
|
<0>,
|
||
|
|
<0>;
|
||
|
|
#dma-cells = <1>;
|
||
|
|
iommus = <&sio_dart 2>;
|
||
|
|
power-domains = <&ps_sio_adma>;
|
||
|
|
resets = <&ps_audio_p>;
|
||
|
|
};
|
||
|
|
|
||
|
|
mca: i2s@238400000 {
|
||
|
|
compatible = "apple,t8103-mca", "apple,mca";
|
||
|
|
reg = <0x2 0x38400000 0x0 0x18000>,
|
||
|
|
<0x2 0x38300000 0x0 0x30000>;
|
||
|
|
|
||
|
|
interrupt-parent = <&aic>;
|
||
|
|
interrupts = <AIC_IRQ 619 IRQ_TYPE_LEVEL_HIGH>,
|
||
|
|
<AIC_IRQ 620 IRQ_TYPE_LEVEL_HIGH>,
|
||
|
|
<AIC_IRQ 621 IRQ_TYPE_LEVEL_HIGH>,
|
||
|
|
<AIC_IRQ 622 IRQ_TYPE_LEVEL_HIGH>,
|
||
|
|
<AIC_IRQ 623 IRQ_TYPE_LEVEL_HIGH>,
|
||
|
|
<AIC_IRQ 624 IRQ_TYPE_LEVEL_HIGH>;
|
||
|
|
|
||
|
|
resets = <&ps_audio_p>;
|
||
|
|
clocks = <&nco 0>, <&nco 1>, <&nco 2>,
|
||
|
|
<&nco 3>, <&nco 4>, <&nco 4>;
|
||
|
|
power-domains = <&ps_audio_p>, <&ps_mca0>, <&ps_mca1>,
|
||
|
|
<&ps_mca2>, <&ps_mca3>, <&ps_mca4>, <&ps_mca5>;
|
||
|
|
dmas = <&admac 0>, <&admac 1>, <&admac 2>, <&admac 3>,
|
||
|
|
<&admac 4>, <&admac 5>, <&admac 6>, <&admac 7>,
|
||
|
|
<&admac 8>, <&admac 9>, <&admac 10>, <&admac 11>,
|
||
|
|
<&admac 12>, <&admac 13>, <&admac 14>, <&admac 15>,
|
||
|
|
<&admac 16>, <&admac 17>, <&admac 18>, <&admac 19>,
|
||
|
|
<&admac 20>, <&admac 21>, <&admac 22>, <&admac 23>;
|
||
|
|
dma-names = "tx0a", "rx0a", "tx0b", "rx0b",
|
||
|
|
"tx1a", "rx1a", "tx1b", "rx1b",
|
||
|
|
"tx2a", "rx2a", "tx2b", "rx2b",
|
||
|
|
"tx3a", "rx3a", "tx3b", "rx3b",
|
||
|
|
"tx4a", "rx4a", "tx4b", "rx4b",
|
||
|
|
"tx5a", "rx5a", "tx5b", "rx5b";
|
||
|
|
|
||
|
|
#sound-dai-cells = <1>;
|
||
|
|
};
|
||
|
|
|
||
|
|
nco: clock-controller@23b044000 {
|
||
|
|
compatible = "apple,t8103-nco", "apple,nco";
|
||
|
|
reg = <0x2 0x3b044000 0x0 0x14000>;
|
||
|
|
clocks = <&nco_clkref>;
|
||
|
|
#clock-cells = <1>;
|
||
|
|
};
|
||
|
|
|
||
|
|
aic: interrupt-controller@23b100000 {
|
||
|
|
compatible = "apple,t8103-aic", "apple,aic";
|
||
|
|
#interrupt-cells = <3>;
|
||
|
|
interrupt-controller;
|
||
|
|
reg = <0x2 0x3b100000 0x0 0x8000>;
|
||
|
|
power-domains = <&ps_aic>;
|
||
|
|
|
||
|
|
affinities {
|
||
|
|
e-core-pmu-affinity {
|
||
|
|
apple,fiq-index = <AIC_CPU_PMU_E>;
|
||
|
|
cpus = <&cpu_e0 &cpu_e1 &cpu_e2 &cpu_e3>;
|
||
|
|
};
|
||
|
|
|
||
|
|
p-core-pmu-affinity {
|
||
|
|
apple,fiq-index = <AIC_CPU_PMU_P>;
|
||
|
|
cpus = <&cpu_p0 &cpu_p1 &cpu_p2 &cpu_p3>;
|
||
|
|
};
|
||
|
|
};
|
||
|
|
};
|
||
|
|
|
||
|
|
pmgr: power-management@23b700000 {
|
||
|
|
compatible = "apple,t8103-pmgr", "apple,pmgr", "syscon", "simple-mfd";
|
||
|
|
#address-cells = <1>;
|
||
|
|
#size-cells = <1>;
|
||
|
|
reg = <0x2 0x3b700000 0 0x14000>;
|
||
|
|
};
|
||
|
|
|
||
|
|
pinctrl_ap: pinctrl@23c100000 {
|
||
|
|
compatible = "apple,t8103-pinctrl", "apple,pinctrl";
|
||
|
|
reg = <0x2 0x3c100000 0x0 0x100000>;
|
||
|
|
power-domains = <&ps_gpio>;
|
||
|
|
|
||
|
|
gpio-controller;
|
||
|
|
#gpio-cells = <2>;
|
||
|
|
gpio-ranges = <&pinctrl_ap 0 0 212>;
|
||
|
|
apple,npins = <212>;
|
||
|
|
|
||
|
|
interrupt-controller;
|
||
|
|
#interrupt-cells = <2>;
|
||
|
|
interrupt-parent = <&aic>;
|
||
|
|
interrupts = <AIC_IRQ 190 IRQ_TYPE_LEVEL_HIGH>,
|
||
|
|
<AIC_IRQ 191 IRQ_TYPE_LEVEL_HIGH>,
|
||
|
|
<AIC_IRQ 192 IRQ_TYPE_LEVEL_HIGH>,
|
||
|
|
<AIC_IRQ 193 IRQ_TYPE_LEVEL_HIGH>,
|
||
|
|
<AIC_IRQ 194 IRQ_TYPE_LEVEL_HIGH>,
|
||
|
|
<AIC_IRQ 195 IRQ_TYPE_LEVEL_HIGH>,
|
||
|
|
<AIC_IRQ 196 IRQ_TYPE_LEVEL_HIGH>;
|
||
|
|
|
||
|
|
i2c0_pins: i2c0-pins {
|
||
|
|
pinmux = <APPLE_PINMUX(192, 1)>,
|
||
|
|
<APPLE_PINMUX(188, 1)>;
|
||
|
|
};
|
||
|
|
|
||
|
|
i2c1_pins: i2c1-pins {
|
||
|
|
pinmux = <APPLE_PINMUX(201, 1)>,
|
||
|
|
<APPLE_PINMUX(199, 1)>;
|
||
|
|
};
|
||
|
|
|
||
|
|
i2c2_pins: i2c2-pins {
|
||
|
|
pinmux = <APPLE_PINMUX(163, 1)>,
|
||
|
|
<APPLE_PINMUX(162, 1)>;
|
||
|
|
};
|
||
|
|
|
||
|
|
i2c3_pins: i2c3-pins {
|
||
|
|
pinmux = <APPLE_PINMUX(73, 1)>,
|
||
|
|
<APPLE_PINMUX(72, 1)>;
|
||
|
|
};
|
||
|
|
|
||
|
|
i2c4_pins: i2c4-pins {
|
||
|
|
pinmux = <APPLE_PINMUX(135, 1)>,
|
||
|
|
<APPLE_PINMUX(134, 1)>;
|
||
|
|
};
|
||
|
|
|
||
|
|
pcie_pins: pcie-pins {
|
||
|
|
pinmux = <APPLE_PINMUX(150, 1)>,
|
||
|
|
<APPLE_PINMUX(151, 1)>,
|
||
|
|
<APPLE_PINMUX(32, 1)>;
|
||
|
|
};
|
||
|
|
};
|
||
|
|
|
||
|
|
pinctrl_nub: pinctrl@23d1f0000 {
|
||
|
|
compatible = "apple,t8103-pinctrl", "apple,pinctrl";
|
||
|
|
reg = <0x2 0x3d1f0000 0x0 0x4000>;
|
||
|
|
power-domains = <&ps_nub_gpio>;
|
||
|
|
|
||
|
|
gpio-controller;
|
||
|
|
#gpio-cells = <2>;
|
||
|
|
gpio-ranges = <&pinctrl_nub 0 0 23>;
|
||
|
|
apple,npins = <23>;
|
||
|
|
|
||
|
|
interrupt-controller;
|
||
|
|
#interrupt-cells = <2>;
|
||
|
|
interrupt-parent = <&aic>;
|
||
|
|
interrupts = <AIC_IRQ 330 IRQ_TYPE_LEVEL_HIGH>,
|
||
|
|
<AIC_IRQ 331 IRQ_TYPE_LEVEL_HIGH>,
|
||
|
|
<AIC_IRQ 332 IRQ_TYPE_LEVEL_HIGH>,
|
||
|
|
<AIC_IRQ 333 IRQ_TYPE_LEVEL_HIGH>,
|
||
|
|
<AIC_IRQ 334 IRQ_TYPE_LEVEL_HIGH>,
|
||
|
|
<AIC_IRQ 335 IRQ_TYPE_LEVEL_HIGH>,
|
||
|
|
<AIC_IRQ 336 IRQ_TYPE_LEVEL_HIGH>;
|
||
|
|
};
|
||
|
|
|
||
|
|
pmgr_mini: power-management@23d280000 {
|
||
|
|
compatible = "apple,t8103-pmgr", "apple,pmgr", "syscon", "simple-mfd";
|
||
|
|
#address-cells = <1>;
|
||
|
|
#size-cells = <1>;
|
||
|
|
reg = <0x2 0x3d280000 0 0x4000>;
|
||
|
|
};
|
||
|
|
|
||
|
|
wdt: watchdog@23d2b0000 {
|
||
|
|
compatible = "apple,t8103-wdt", "apple,wdt";
|
||
|
|
reg = <0x2 0x3d2b0000 0x0 0x4000>;
|
||
|
|
clocks = <&clkref>;
|
||
|
|
interrupt-parent = <&aic>;
|
||
|
|
interrupts = <AIC_IRQ 338 IRQ_TYPE_LEVEL_HIGH>;
|
||
|
|
};
|
||
|
|
|
||
|
|
pinctrl_smc: pinctrl@23e820000 {
|
||
|
|
compatible = "apple,t8103-pinctrl", "apple,pinctrl";
|
||
|
|
reg = <0x2 0x3e820000 0x0 0x4000>;
|
||
|
|
|
||
|
|
gpio-controller;
|
||
|
|
#gpio-cells = <2>;
|
||
|
|
gpio-ranges = <&pinctrl_smc 0 0 16>;
|
||
|
|
apple,npins = <16>;
|
||
|
|
|
||
|
|
interrupt-controller;
|
||
|
|
#interrupt-cells = <2>;
|
||
|
|
interrupt-parent = <&aic>;
|
||
|
|
interrupts = <AIC_IRQ 391 IRQ_TYPE_LEVEL_HIGH>,
|
||
|
|
<AIC_IRQ 392 IRQ_TYPE_LEVEL_HIGH>,
|
||
|
|
<AIC_IRQ 393 IRQ_TYPE_LEVEL_HIGH>,
|
||
|
|
<AIC_IRQ 394 IRQ_TYPE_LEVEL_HIGH>,
|
||
|
|
<AIC_IRQ 395 IRQ_TYPE_LEVEL_HIGH>,
|
||
|
|
<AIC_IRQ 396 IRQ_TYPE_LEVEL_HIGH>,
|
||
|
|
<AIC_IRQ 397 IRQ_TYPE_LEVEL_HIGH>;
|
||
|
|
};
|
||
|
|
|
||
|
|
pinctrl_aop: pinctrl@24a820000 {
|
||
|
|
compatible = "apple,t8103-pinctrl", "apple,pinctrl";
|
||
|
|
reg = <0x2 0x4a820000 0x0 0x4000>;
|
||
|
|
|
||
|
|
gpio-controller;
|
||
|
|
#gpio-cells = <2>;
|
||
|
|
gpio-ranges = <&pinctrl_aop 0 0 42>;
|
||
|
|
apple,npins = <42>;
|
||
|
|
|
||
|
|
interrupt-controller;
|
||
|
|
#interrupt-cells = <2>;
|
||
|
|
interrupt-parent = <&aic>;
|
||
|
|
interrupts = <AIC_IRQ 268 IRQ_TYPE_LEVEL_HIGH>,
|
||
|
|
<AIC_IRQ 269 IRQ_TYPE_LEVEL_HIGH>,
|
||
|
|
<AIC_IRQ 270 IRQ_TYPE_LEVEL_HIGH>,
|
||
|
|
<AIC_IRQ 271 IRQ_TYPE_LEVEL_HIGH>,
|
||
|
|
<AIC_IRQ 272 IRQ_TYPE_LEVEL_HIGH>,
|
||
|
|
<AIC_IRQ 273 IRQ_TYPE_LEVEL_HIGH>,
|
||
|
|
<AIC_IRQ 274 IRQ_TYPE_LEVEL_HIGH>;
|
||
|
|
};
|
||
|
|
|
||
|
|
ans_mbox: mbox@277408000 {
|
||
|
|
compatible = "apple,t8103-asc-mailbox", "apple,asc-mailbox-v4";
|
||
|
|
reg = <0x2 0x77408000 0x0 0x4000>;
|
||
|
|
interrupt-parent = <&aic>;
|
||
|
|
interrupts = <AIC_IRQ 583 IRQ_TYPE_LEVEL_HIGH>,
|
||
|
|
<AIC_IRQ 584 IRQ_TYPE_LEVEL_HIGH>,
|
||
|
|
<AIC_IRQ 585 IRQ_TYPE_LEVEL_HIGH>,
|
||
|
|
<AIC_IRQ 586 IRQ_TYPE_LEVEL_HIGH>;
|
||
|
|
interrupt-names = "send-empty", "send-not-empty",
|
||
|
|
"recv-empty", "recv-not-empty";
|
||
|
|
#mbox-cells = <0>;
|
||
|
|
power-domains = <&ps_ans2>;
|
||
|
|
};
|
||
|
|
|
||
|
|
sart: iommu@27bc50000 {
|
||
|
|
compatible = "apple,t8103-sart";
|
||
|
|
reg = <0x2 0x7bc50000 0x0 0x10000>;
|
||
|
|
power-domains = <&ps_ans2>;
|
||
|
|
};
|
||
|
|
|
||
|
|
nvme@27bcc0000 {
|
||
|
|
compatible = "apple,t8103-nvme-ans2", "apple,nvme-ans2";
|
||
|
|
reg = <0x2 0x7bcc0000 0x0 0x40000>,
|
||
|
|
<0x2 0x77400000 0x0 0x4000>;
|
||
|
|
reg-names = "nvme", "ans";
|
||
|
|
interrupt-parent = <&aic>;
|
||
|
|
interrupts = <AIC_IRQ 590 IRQ_TYPE_LEVEL_HIGH>;
|
||
|
|
mboxes = <&ans_mbox>;
|
||
|
|
apple,sart = <&sart>;
|
||
|
|
power-domains = <&ps_ans2>, <&ps_apcie_st>;
|
||
|
|
power-domain-names = "ans", "apcie0";
|
||
|
|
resets = <&ps_ans2>;
|
||
|
|
};
|
||
|
|
|
||
|
|
pcie0_dart_0: iommu@681008000 {
|
||
|
|
compatible = "apple,t8103-dart";
|
||
|
|
reg = <0x6 0x81008000 0x0 0x4000>;
|
||
|
|
#iommu-cells = <1>;
|
||
|
|
interrupt-parent = <&aic>;
|
||
|
|
interrupts = <AIC_IRQ 696 IRQ_TYPE_LEVEL_HIGH>;
|
||
|
|
power-domains = <&ps_apcie_gp>;
|
||
|
|
};
|
||
|
|
|
||
|
|
pcie0_dart_1: iommu@682008000 {
|
||
|
|
compatible = "apple,t8103-dart";
|
||
|
|
reg = <0x6 0x82008000 0x0 0x4000>;
|
||
|
|
#iommu-cells = <1>;
|
||
|
|
interrupt-parent = <&aic>;
|
||
|
|
interrupts = <AIC_IRQ 699 IRQ_TYPE_LEVEL_HIGH>;
|
||
|
|
power-domains = <&ps_apcie_gp>;
|
||
|
|
status = "disabled";
|
||
|
|
};
|
||
|
|
|
||
|
|
pcie0_dart_2: iommu@683008000 {
|
||
|
|
compatible = "apple,t8103-dart";
|
||
|
|
reg = <0x6 0x83008000 0x0 0x4000>;
|
||
|
|
#iommu-cells = <1>;
|
||
|
|
interrupt-parent = <&aic>;
|
||
|
|
interrupts = <AIC_IRQ 702 IRQ_TYPE_LEVEL_HIGH>;
|
||
|
|
power-domains = <&ps_apcie_gp>;
|
||
|
|
status = "disabled";
|
||
|
|
};
|
||
|
|
|
||
|
|
pcie0: pcie@690000000 {
|
||
|
|
compatible = "apple,t8103-pcie", "apple,pcie";
|
||
|
|
device_type = "pci";
|
||
|
|
|
||
|
|
reg = <0x6 0x90000000 0x0 0x1000000>,
|
||
|
|
<0x6 0x80000000 0x0 0x100000>,
|
||
|
|
<0x6 0x81000000 0x0 0x4000>,
|
||
|
|
<0x6 0x82000000 0x0 0x4000>,
|
||
|
|
<0x6 0x83000000 0x0 0x4000>;
|
||
|
|
reg-names = "config", "rc", "port0", "port1", "port2";
|
||
|
|
|
||
|
|
interrupt-parent = <&aic>;
|
||
|
|
interrupts = <AIC_IRQ 695 IRQ_TYPE_LEVEL_HIGH>,
|
||
|
|
<AIC_IRQ 698 IRQ_TYPE_LEVEL_HIGH>,
|
||
|
|
<AIC_IRQ 701 IRQ_TYPE_LEVEL_HIGH>;
|
||
|
|
|
||
|
|
msi-controller;
|
||
|
|
msi-parent = <&pcie0>;
|
||
|
|
msi-ranges = <&aic AIC_IRQ 704 IRQ_TYPE_EDGE_RISING 32>;
|
||
|
|
|
||
|
|
|
||
|
|
iommu-map = <0x100 &pcie0_dart_0 1 1>,
|
||
|
|
<0x200 &pcie0_dart_1 1 1>,
|
||
|
|
<0x300 &pcie0_dart_2 1 1>;
|
||
|
|
iommu-map-mask = <0xff00>;
|
||
|
|
|
||
|
|
bus-range = <0 3>;
|
||
|
|
#address-cells = <3>;
|
||
|
|
#size-cells = <2>;
|
||
|
|
ranges = <0x43000000 0x6 0xa0000000 0x6 0xa0000000 0x0 0x20000000>,
|
||
|
|
<0x02000000 0x0 0xc0000000 0x6 0xc0000000 0x0 0x40000000>;
|
||
|
|
|
||
|
|
power-domains = <&ps_apcie_gp>;
|
||
|
|
pinctrl-0 = <&pcie_pins>;
|
||
|
|
pinctrl-names = "default";
|
||
|
|
|
||
|
|
port00: pci@0,0 {
|
||
|
|
device_type = "pci";
|
||
|
|
reg = <0x0 0x0 0x0 0x0 0x0>;
|
||
|
|
reset-gpios = <&pinctrl_ap 152 GPIO_ACTIVE_LOW>;
|
||
|
|
|
||
|
|
#address-cells = <3>;
|
||
|
|
#size-cells = <2>;
|
||
|
|
ranges;
|
||
|
|
|
||
|
|
interrupt-controller;
|
||
|
|
#interrupt-cells = <1>;
|
||
|
|
|
||
|
|
interrupt-map-mask = <0 0 0 7>;
|
||
|
|
interrupt-map = <0 0 0 1 &port00 0 0 0 0>,
|
||
|
|
<0 0 0 2 &port00 0 0 0 1>,
|
||
|
|
<0 0 0 3 &port00 0 0 0 2>,
|
||
|
|
<0 0 0 4 &port00 0 0 0 3>;
|
||
|
|
};
|
||
|
|
|
||
|
|
port01: pci@1,0 {
|
||
|
|
device_type = "pci";
|
||
|
|
reg = <0x800 0x0 0x0 0x0 0x0>;
|
||
|
|
reset-gpios = <&pinctrl_ap 153 GPIO_ACTIVE_LOW>;
|
||
|
|
|
||
|
|
#address-cells = <3>;
|
||
|
|
#size-cells = <2>;
|
||
|
|
ranges;
|
||
|
|
|
||
|
|
interrupt-controller;
|
||
|
|
#interrupt-cells = <1>;
|
||
|
|
|
||
|
|
interrupt-map-mask = <0 0 0 7>;
|
||
|
|
interrupt-map = <0 0 0 1 &port01 0 0 0 0>,
|
||
|
|
<0 0 0 2 &port01 0 0 0 1>,
|
||
|
|
<0 0 0 3 &port01 0 0 0 2>,
|
||
|
|
<0 0 0 4 &port01 0 0 0 3>;
|
||
|
|
status = "disabled";
|
||
|
|
};
|
||
|
|
|
||
|
|
port02: pci@2,0 {
|
||
|
|
device_type = "pci";
|
||
|
|
reg = <0x1000 0x0 0x0 0x0 0x0>;
|
||
|
|
reset-gpios = <&pinctrl_ap 33 GPIO_ACTIVE_LOW>;
|
||
|
|
|
||
|
|
#address-cells = <3>;
|
||
|
|
#size-cells = <2>;
|
||
|
|
ranges;
|
||
|
|
|
||
|
|
interrupt-controller;
|
||
|
|
#interrupt-cells = <1>;
|
||
|
|
|
||
|
|
interrupt-map-mask = <0 0 0 7>;
|
||
|
|
interrupt-map = <0 0 0 1 &port02 0 0 0 0>,
|
||
|
|
<0 0 0 2 &port02 0 0 0 1>,
|
||
|
|
<0 0 0 3 &port02 0 0 0 2>,
|
||
|
|
<0 0 0 4 &port02 0 0 0 3>;
|
||
|
|
status = "disabled";
|
||
|
|
};
|
||
|
|
};
|
||
|
|
};
|
||
|
|
};
|
||
|
|
|
||
|
|
#include "t8103-pmgr.dtsi"
|