130 lines
2.4 KiB
Plaintext
130 lines
2.4 KiB
Plaintext
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// SPDX-License-Identifier: GPL-2.0+
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/*
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* Device Tree file for the Kontron SMARC-sAL28 board on a SMARC Eval 2.0
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* carrier (ADS2).
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*
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* Copyright (C) 2019 Michael Walle <michael@walle.cc>
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*
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*/
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/dts-v1/;
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#include <dt-bindings/clock/fsl,qoriq-clockgen.h>
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#include "fsl-ls1028a-kontron-sl28.dts"
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/ {
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model = "Kontron SMARC-sAL28 (Single PHY) on SMARC Eval 2.0 carrier";
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compatible = "kontron,sl28-var3-ads2", "kontron,sl28-var3",
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"kontron,sl28", "fsl,ls1028a";
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pwm-fan {
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compatible = "pwm-fan";
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cooling-min-state = <0>;
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cooling-max-state = <3>;
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#cooling-cells = <2>;
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pwms = <&sl28cpld_pwm0 0 4000000>;
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cooling-levels = <1 128 192 255>;
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};
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sound {
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#address-cells = <1>;
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#size-cells = <0>;
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compatible = "simple-audio-card";
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simple-audio-card,widgets =
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"Headphone", "Headphone Jack",
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"Line", "Line Out Jack",
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"Microphone", "Microphone Jack",
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"Line", "Line In Jack";
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simple-audio-card,routing =
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"Line Out Jack", "LINEOUTR",
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"Line Out Jack", "LINEOUTL",
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"Headphone Jack", "HPOUTR",
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"Headphone Jack", "HPOUTL",
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"IN1L", "Line In Jack",
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"IN1R", "Line In Jack",
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"Microphone Jack", "MICBIAS",
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"IN2L", "Microphone Jack",
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"IN2R", "Microphone Jack";
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simple-audio-card,mclk-fs = <256>;
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simple-audio-card,dai-link@0 {
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reg = <0>;
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bitclock-master = <&dailink0_master>;
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frame-master = <&dailink0_master>;
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format = "i2s";
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cpu {
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sound-dai = <&sai6>;
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};
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dailink0_master: codec {
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sound-dai = <&wm8904>;
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};
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};
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simple-audio-card,dai-link@1 {
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reg = <1>;
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bitclock-master = <&dailink1_master>;
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frame-master = <&dailink1_master>;
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format = "i2s";
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cpu {
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sound-dai = <&sai5>;
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};
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dailink1_master: codec {
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sound-dai = <&wm8904>;
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};
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};
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};
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};
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&dspi2 {
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flash@0 {
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compatible = "jedec,spi-nor";
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m25p,fast-read;
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spi-max-frequency = <100000000>;
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reg = <0>;
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};
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};
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&i2c3 {
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eeprom@57 {
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compatible = "atmel,24c64";
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reg = <0x57>;
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pagesize = <32>;
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};
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};
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&i2c4 {
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status = "okay";
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wm8904: audio-codec@1a {
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#sound-dai-cells = <0>;
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compatible = "wlf,wm8904";
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reg = <0x1a>;
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clocks = <&mclk>;
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clock-names = "mclk";
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assigned-clocks = <&mclk>;
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assigned-clock-rates = <1250000>;
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};
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};
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&sai5 {
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status = "okay";
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};
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&sai6 {
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status = "okay";
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};
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&soc {
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mclk: clock-mclk@f130080 {
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compatible = "fsl,vf610-sai-clock";
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reg = <0x0 0xf130080 0x0 0x80>;
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clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
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QORIQ_CLK_PLL_DIV(2)>;
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#clock-cells = <0>;
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};
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};
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