95 lines
1.7 KiB
Plaintext
95 lines
1.7 KiB
Plaintext
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// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
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/*
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* Device Tree file for Freescale LS2080a RDB Board.
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*
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* Copyright 2016 Freescale Semiconductor, Inc.
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* Copyright 2017 NXP
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*
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* Abhimanyu Saini <abhimanyu.saini@nxp.com>
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* Bhupesh Sharma <bhupesh.sharma@freescale.com>
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*
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*/
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/dts-v1/;
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#include "fsl-ls2080a.dtsi"
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#include "fsl-ls208xa-rdb.dtsi"
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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/ {
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model = "Freescale Layerscape 2080a RDB Board";
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compatible = "fsl,ls2080a-rdb", "fsl,ls2080a";
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chosen {
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stdout-path = "serial1:115200n8";
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};
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};
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&dpmac5 {
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phy-handle = <&mdio2_phy1>;
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phy-connection-type = "10gbase-r";
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};
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&dpmac6 {
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phy-handle = <&mdio2_phy2>;
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phy-connection-type = "10gbase-r";
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};
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&dpmac7 {
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phy-handle = <&mdio2_phy3>;
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phy-connection-type = "10gbase-r";
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};
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&dpmac8 {
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phy-handle = <&mdio2_phy4>;
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phy-connection-type = "10gbase-r";
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};
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&emdio1 {
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status = "disabled";
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/* CS4340 PHYs */
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mdio1_phy1: emdio1-phy@10 {
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reg = <0x10>;
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};
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mdio1_phy2: emdio1-phy@11 {
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reg = <0x11>;
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};
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mdio1_phy3: emdio1-phy@12 {
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reg = <0x12>;
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};
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mdio1_phy4: emdio1-phy@13 {
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reg = <0x13>;
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};
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};
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&emdio2 {
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/* AQR405 PHYs */
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mdio2_phy1: emdio2-phy@0 {
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compatible = "ethernet-phy-ieee802.3-c45";
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interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
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reg = <0x0>;
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};
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mdio2_phy2: emdio2-phy@1 {
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compatible = "ethernet-phy-ieee802.3-c45";
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interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
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reg = <0x1>;
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};
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mdio2_phy3: emdio2-phy@2 {
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compatible = "ethernet-phy-ieee802.3-c45";
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interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
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reg = <0x2>;
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};
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mdio2_phy4: emdio2-phy@3 {
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compatible = "ethernet-phy-ieee802.3-c45";
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interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
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reg = <0x3>;
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};
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};
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