69 lines
1.7 KiB
Plaintext
69 lines
1.7 KiB
Plaintext
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// SPDX-License-Identifier: GPL-2.0+
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/*
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* Copyright 2018-2019 NXP
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* Dong Aisheng <aisheng.dong@nxp.com>
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*/
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#include <dt-bindings/clock/imx8-lpcg.h>
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#include <dt-bindings/firmware/imx/rsrc.h>
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audio_subsys: bus@59000000 {
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compatible = "simple-bus";
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#address-cells = <1>;
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#size-cells = <1>;
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ranges = <0x59000000 0x0 0x59000000 0x1000000>;
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audio_ipg_clk: clock-audio-ipg {
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compatible = "fixed-clock";
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#clock-cells = <0>;
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clock-frequency = <120000000>;
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clock-output-names = "audio_ipg_clk";
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};
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dsp_lpcg: clock-controller@59580000 {
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compatible = "fsl,imx8qxp-lpcg";
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reg = <0x59580000 0x10000>;
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#clock-cells = <1>;
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clocks = <&audio_ipg_clk>,
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<&audio_ipg_clk>,
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<&audio_ipg_clk>;
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clock-indices = <IMX_LPCG_CLK_4>, <IMX_LPCG_CLK_5>,
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<IMX_LPCG_CLK_7>;
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clock-output-names = "dsp_lpcg_adb_clk",
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"dsp_lpcg_ipg_clk",
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"dsp_lpcg_core_clk";
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power-domains = <&pd IMX_SC_R_DSP>;
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};
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dsp_ram_lpcg: clock-controller@59590000 {
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compatible = "fsl,imx8qxp-lpcg";
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reg = <0x59590000 0x10000>;
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#clock-cells = <1>;
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clocks = <&audio_ipg_clk>;
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clock-indices = <IMX_LPCG_CLK_4>;
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clock-output-names = "dsp_ram_lpcg_ipg_clk";
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power-domains = <&pd IMX_SC_R_DSP_RAM>;
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};
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dsp: dsp@596e8000 {
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compatible = "fsl,imx8qxp-dsp";
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reg = <0x596e8000 0x88000>;
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clocks = <&dsp_lpcg IMX_LPCG_CLK_5>,
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<&dsp_ram_lpcg IMX_LPCG_CLK_4>,
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<&dsp_lpcg IMX_LPCG_CLK_7>;
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clock-names = "ipg", "ocram", "core";
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power-domains = <&pd IMX_SC_R_MU_13A>,
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<&pd IMX_SC_R_MU_13B>,
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<&pd IMX_SC_R_DSP>,
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<&pd IMX_SC_R_DSP_RAM>;
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mbox-names = "txdb0", "txdb1",
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"rxdb0", "rxdb1";
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mboxes = <&lsio_mu13 2 0>,
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<&lsio_mu13 2 1>,
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<&lsio_mu13 3 0>,
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<&lsio_mu13 3 1>;
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memory-region = <&dsp_reserved>;
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status = "disabled";
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};
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};
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