75 lines
1.8 KiB
Plaintext
75 lines
1.8 KiB
Plaintext
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// SPDX-License-Identifier: GPL-2.0+
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/*
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* Copyright 2021 NXP
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* Dong Aisheng <aisheng.dong@nxp.com>
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*/
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vpu: vpu@2c000000 {
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#address-cells = <1>;
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#size-cells = <1>;
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ranges = <0x2c000000 0x0 0x2c000000 0x2000000>;
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reg = <0 0x2c000000 0 0x1000000>;
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power-domains = <&pd IMX_SC_R_VPU>;
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status = "disabled";
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mu_m0: mailbox@2d000000 {
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compatible = "fsl,imx6sx-mu";
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reg = <0x2d000000 0x20000>;
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interrupts = <GIC_SPI 469 IRQ_TYPE_LEVEL_HIGH>;
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#mbox-cells = <2>;
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power-domains = <&pd IMX_SC_R_VPU_MU_0>;
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status = "disabled";
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};
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mu1_m0: mailbox@2d020000 {
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compatible = "fsl,imx6sx-mu";
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reg = <0x2d020000 0x20000>;
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interrupts = <GIC_SPI 470 IRQ_TYPE_LEVEL_HIGH>;
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#mbox-cells = <2>;
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power-domains = <&pd IMX_SC_R_VPU_MU_1>;
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status = "disabled";
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};
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mu2_m0: mailbox@2d040000 {
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compatible = "fsl,imx6sx-mu";
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reg = <0x2d040000 0x20000>;
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interrupts = <GIC_SPI 474 IRQ_TYPE_LEVEL_HIGH>;
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#mbox-cells = <2>;
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power-domains = <&pd IMX_SC_R_VPU_MU_2>;
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status = "disabled";
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};
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vpu_core0: vpu-core@2d080000 {
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reg = <0x2d080000 0x10000>;
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compatible = "nxp,imx8q-vpu-decoder";
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power-domains = <&pd IMX_SC_R_VPU_DEC_0>;
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mbox-names = "tx0", "tx1", "rx";
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mboxes = <&mu_m0 0 0>,
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<&mu_m0 0 1>,
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<&mu_m0 1 0>;
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status = "disabled";
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};
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vpu_core1: vpu-core@2d090000 {
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reg = <0x2d090000 0x10000>;
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compatible = "nxp,imx8q-vpu-encoder";
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power-domains = <&pd IMX_SC_R_VPU_ENC_0>;
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mbox-names = "tx0", "tx1", "rx";
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mboxes = <&mu1_m0 0 0>,
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<&mu1_m0 0 1>,
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<&mu1_m0 1 0>;
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status = "disabled";
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};
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vpu_core2: vpu-core@2d0a0000 {
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reg = <0x2d0a0000 0x10000>;
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compatible = "nxp,imx8q-vpu-encoder";
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power-domains = <&pd IMX_SC_R_VPU_ENC_1>;
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mbox-names = "tx0", "tx1", "rx";
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mboxes = <&mu2_m0 0 0>,
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<&mu2_m0 0 1>,
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<&mu2_m0 1 0>;
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status = "disabled";
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};
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};
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